Abstract: A process for fabricating a recessed field oxide area comprises providing a substrate having isolation stacks and first and second recesses having openings therein, the first recesses being wider than the second recesses. The recesses can have a depth in the approximate range of 200.ANG.-3000.ANG.. Next, the first and second recesses are lined with nitride, and the substrate is blanketed with a conformal material which bridges the openings of the second recesses but not the openings of the first recesses. The conformal material and the nitride is removed from horizontal surfaces of the isolation stacks, and essentially all of the conformal material is removed from the first recesses. At least a portion of the conformal material is left in the second recesses. Subsequent to the step of removing the conformal material, the substrate and the conformal material is oxidized to create field oxide areas at the first and second recesses.

Abstract: A process for forming field oxide on a semiconductor substrate having reduced field oxide thinning comprises forming of an oxide layer over a semiconductor substrate, and forming a protective layer over the oxide layer. A mask is formed over the protective layer thereby forming exposed and covered regions of the protective layer. The exposed portions of the protective layer are removed to form at least first, second, and third disconnected protective structures, wherein the distance between the first and second protective structures is smaller than the distance between the second and third protective structures. The oxide layer and a portion of the substrate between the protective structures is removed to expose a portion of the substrate. A blanket polycrystalline silicon (poly) layer is formed over the substrate, and the poly layer is isotropically etched to remove the poly from between the second and third protective structures and leave a portion of the poly between the first and second structures.

Abstract: A process for reducing stress during processing of semiconductor wafers comprising the steps of depositing a masking stack on a top and a bottom surface of the wafer and then removing at least a portion of the masking stack on the bottom surface prior to forming isolation regions on the top surface of the semiconductor wafer. In one embodiment, silicon nitride is formed on the top and the bottom surface of a silicon wafer. The silicon nitride is then patterned and etched on the top surface of the wafer to expose regions of the underlying silicon for field oxide formation. Prior to the field oxidation formation on the top side of the wafer, the silicon nitride layer on the bottom side of the wafer is removed so that a layer of silicon dioxide is formed on the bottom surface of the wafer during field oxidation formation.

Abstract: A process for doping hemispherical grain silicon is provided and includes the steps of providing hemispherical grain silicon and a source of a dopant material and exposing the hemispherical grain silicon to the dopant material at a temperature less than the formation temperature of the hemispherical grain silicon for a time and at a pressure sufficient for diffusion of the dopant material into the hemispherical grain silicon to occur. The grain size of the HSG silicon is not adversely affected (i.e., reduced in size or changed in shape) by eliminating the need for a high temperature annealing step.

Abstract: A method of forming field oxide during the manufacture of a semiconductor device comprises the steps of providing a semiconductor wafer having a plurality of recesses or trenches therein. A layer of texturized polycrystalline silicon is formed within the recesses, which is subsequently oxidized to form field oxide. The instant method reduces stress imparted to the die as the texturized polycrystalline silicon has voids or holes which absorb the expanding volume as the silicon is oxidized to form field oxide.

Abstract: A semiconductor wafer having a first layer and overlying insulating layer receives a photoresist layer. A first photoresist area is exposed to light having a first dosage, while a second, adjacent photoresist area is concurrently exposed to light having a second dosage. The first area and second area then are concurrently developed to partially expose the photoresist layer. The partial exposure removes photoresist within the first area to one depth and within the second area to a second depth. The second depth differs from the first depth. In one embodiment the second depth extends through the photoresist down to the insulating layer. After subsequently performing a contact and/or trench etch through the exposed insulating layer and removing excess photoresist above the insulating layer, conductive material is deposited in the contact/trench opening and over the insulating layer. The result is an upper conductive layer coupled to the first layer via a contact or other conductive connection.

Abstract: A semiconductor processing method of forming a pair of adjacent field oxide regions includes, i) providing a sacrificial pad oxide layer to a thickness of from 20 Angstroms to 100 Angstroms; ii) providing a patterned masking layer over the sacrificial pad oxide layer and over a desired active area region, the layer having a thickness of from 500 Angstroms to 3000 Angstroms and comprising a pair of adjacent masking blocks having a minimum pitch of from 0.5 micron to 0.7 micron; iii) oxidizing portions of the substrate unmasked by the masking layer in an O.sub.2 ambient at a pressure of at least 15 atmospheres to form at least one pair of adjacent field oxide regions, the ambient being substantially void of H.sub.

Abstract: A structure and process for forming a contact to a semiconductor substrate on a semiconductor device comprises the step of forming a patterned mask over a semiconductor substrate and over a field oxide region, then etching the semiconductor substrate and the field oxide region to form a trench. The trench comprises a bottom and a first sidewall consisting of silicon and a second sidewall comprising field oxide. The etching step removes a part of a doped region in the substrate. Next, a blanket nitride layer and a blanket oxide layer is formed over the substrate, and a spacer etch is performed on the nitride and oxide layer leaving nitride and oxide over the first and second sidewalls. The trench bottom is oxidized to form a layer of oxide over the bottom of the trench thereby insulating the trench bottom, and the oxide encroaches under the nitride and oxide on the sidewalls to join with the field oxide.

Abstract: This invention is a process flow involving wordline spacer formation and source/drain implants which mitigates stress-induced damage to the silicon substrate during the post-implant anneal step. The process employs composite wordline spacers having a removable silicon dioxide portion and a non-removable silicon nitride portion. The post-implant anneal step is performed with only the silicon nitride portion of the spacer in place on the wordlines. The thinness of the silicon nitride portion greatly reduces the stress levels experienced by the substrate during the anneal as compared with that experienced by the substrate when thick one-piece silicon nitride spacers are left in place during the anneal.

Abstract: A semiconductor processing method of forming a pair of adjacent field oxide regions includes, i) providing a sacrificial pad oxide layer to a thickness of from 20 Angstroms to 100 Angstroms; ii) providing a patterned masking layer over the sacrificial pad oxide layer and over a desired active area region, the layer having a thickness of from 500 Angstroms to 3000 Angstroms and comprising a pair of adjacent masking blocks having a minimum pitch of from 0.5 micron to 0.7 micron; iii) oxidizing portions of the substrate unmasked by the masking layer in an H.sub.2 O steam ambient at a pressure of from about 0.5 atmosphere to about 2 atmospheres and at a temperature of from about 900.degree. C. to about 1200.degree. C.

Abstract: A method for forming a semiconductor device comprises the steps of providing a semiconductor substrate having first and second surfaces, the second surface having an inferior plane with respect to the first surface. An oxidizing-resistant layer such as nitride is formed on the first surface, and an oxidizable material is formed over the first and second surfaces. A protective material is formed over the first and second surfaces, which is then removed from the first surface. Subsequent to the step of removing the protective material from the first surface, the oxidizable material is removed from the first surface and is left over the second surface. Subsequent to the step of removing the oxidizable material from the first surface, the protective material is removed from the second surface and the oxidizable material remains over the second surface. Subsequent to removing the protective material from the second surface, the oxidizable material on the second surface is oxidized.

Abstract: A method of forming a semiconductor device comprises the steps of forming a patterned pad oxide layer having a first nitrogen concentration over a semiconductor substrate assembly such as a semiconductor substrate. The substrate is oxidized to form field oxide which also forms an area of Kooi nitride at the interface of the field oxide and the active area. The Kooi nitride comprises a second nitrogen concentration which is less than the nitrogen concentration of the pad oxide. Next, the pad oxide and the Kooi nitride are oxidized thereby forming gate oxide over the pad oxide. The nitridized pad oxide oxidizes slower than the Kooi nitride, and therefore gate oxide thinning which is known to result from Kooi nitride is reduced or eliminated. Further, the need for the growth of a sacrificial oxide layer to remove the Kooi nitride, and a subsequent strip of the sacrificial oxide is eliminated thereby reducing thinning of the field oxide.

Abstract: A semiconductor processing method of forming an electrically conductive contact plug relative to a wafer includes, a) providing a substrate to which electrical connection is to be made; b) depositing a layer of first material atop the substrate to a selected thickness; c) pattern masking the first material layer for formation of a desired contact opening therethrough; d) etching through the first material layer to form a contact opening therethrough for making electrical connection with the substrate, the contact opening having an outermost region; e) after etching to form the contact opening, removing the masking from the first material layer; f) after removing the masking from the first material layer, facet sputter etching into the first material layer relative to the contact opening to provide outwardly angled sidewalls which effectively widen the contact opening outermost region, the outwardly angled sidewalls having an inner base where they join with the original contact opening; g) depositing a layer o

Abstract: A method of reducing diffusion of impurity dopants within a semiconductive material beneath a field effect transistor gate in a process of forming a field effect transistor includes, a) providing a bulk monocrystalline silicon substrate; b) providing a gate oxide layer over the silicon substrate; c) providing a patterned gate over the gate oxide layer, the gate having sidewalls; d) providing a pair of diffusion regions within the silicon substrate adjacent the gate sidewalls; and e) subjecting the wafer to an oxidizing atmosphere at a pressure of from about 5 atmospheres to about 30 atmospheres and at a temperature of from about 650.degree. C. to about 750.degree. C. for a period of time from about 5 minutes to about 30 minutes effective, i) to oxidize the gate sidewalls, ii) to oxidize the semiconductive material substrate adjacent the gate sidewalls, and iii) to thicken the gate oxide layer adjacent the gate sidewalls.

Abstract: A semiconductor processing method of forming a field oxide region on a semiconductor substrate includes, a) providing a patterned first masking layer over a desired active area region of a semiconductor substrate, the first masking layer having at least one side edge; b) providing a silicon sidewall spacer over the side edge of the patterned first masking layer, the silicon sidewall spacer having a laterally outward projecting foot portion; c) oxidizing the substrate and the silicon sidewall spacer to form a field oxide region on the substrate; d) stripping the first masking layer from the substrate; and e) providing a gate oxide layer over the substrate. The invention enables taking advantage of process techniques which minimize the size of field oxide bird's beaks without sacrificing upper field oxide topography.

Abstract: A method for forming a semiconductor device comprises the steps of forming an oxide over a silicon layer, forming a blanket first nitride layer over the oxide layer and the silicon layer, and etching the first nitride layer and the oxide layer to form a sidewall from at least the oxide layer and the first nitride layer. Next, a second nitride layer is formed over the sidewall and an oxidizable layer is formed over the second nitride layer. The oxidizable and the second nitride layers are etched to form a spacer from the oxidizable layer and the second nitride layer, and the oxidizable and the silicon layers are etched.

Abstract: A semiconductor processing method of forming an electrically conductive contact plug relative to a wafer includes, a) providing a substrate to which electrical connection is to be made; b) depositing a layer of first material atop the substrate to a selected thickness; c) pattern masking the first material layer for formation of a desired contact opening therethrough; d) etching through the first material layer to form a contact opening therethrough for making electrical connection with the substrate, the contact opening having an outermost region; e) after etching to form the contact opening, removing the masking from the first material layer; f) after removing the masking from the first material layer, facet sputter etching into the first material layer relative to the contact opening to provide outwardly angled sidewalls which effectively widen the contact opening outermost region, the outwardly angled sidewalls having an inner base where they join with the original contact opening; g) depositing a layer o

Abstract: This invention constitutes a process for fabricating a structure which, when incorporated in an integrated circuit, will reduce current leakage into the substrate from transistor source/drain regions. The structure is particularly useful in dynamic random access memories, as it will minimize the effect of alpha particle radiation, thus improving the soft error rate. A trench is etched through the transistor source or drain region. A high dosage of oxygen ions is then implanted at low energy in the floor, but not the sidewalls of the trench. The resulting oxygen-implanted silicon layer at the bottom of the trench is then converted to a silicon dioxide barrier layer through rapid thermal processing or furnace annealing in an inert ambiance. The trench is then lined with a deposited contact layer that is rendered conductive either during or subsequent to deposition. Contact between the contact layer and the source or drain region is made through the sidewalls of the trench, which were not implanted with oxygen.

Abstract: A structure and process for forming a contact to a semiconductor substrate on a semiconductor device comprises the step of forming a patterned mask over a semiconductor substrate and over a field oxide region, then etching the semiconductor substrate and the field oxide region to form a trench. The trench comprises a bottom and a first sidewall consisting of silicon and a second sidewall comprising field oxide. The etching step removes a part of a doped region in the substrate. Next, a blanket nitride layer and a blanket oxide layer is formed over the substrate, and a spacer etch is performed on the nitride and oxide layer leaving nitride and oxide over the first and second sidewalls. The trench bottom is oxidized to form a layer of oxide over the bottom of the trench thereby insulating the trench bottom, and the oxide encroaches under the nitride and oxide on the sidewalls to join with the field oxide.

Abstract: A process useful for isolating active areas of semiconductor devices in which an isolation trench is created in a substrate, the isolation trench being lined with an oxidation barrier and filled with a thick film. An oxidation step is performed in which the thick film is oxidized. The oxidation is self-limiting as the oxidation barrier prevents the substrate surrounding the trench from being oxidized.