Patents by Inventor Nansheng SHEN
Nansheng SHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230301522Abstract: This invention relates to a system and method for monitoring a patient. The method comprises obtaining thermal images from a thermal sensor; obtaining respiratory rate and heart rate measurement from an ultra-wideband (UWB) sensor; analysing the thermal images to determine presence of patient on a bed, temperature and activity intensity; andin response to determining presence of patient on the bed and the activity intensity is below a certain threshold, record the temperature, respiratory rate and heart rate.Type: ApplicationFiled: August 18, 2020Publication date: September 28, 2023Inventors: Swee Yen Tan, Nansheng Shen, ANSHU
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Publication number: 20160308013Abstract: A semiconductor device production method includes preparing a first structure having a first planar semiconductor layer, and a first columnar semiconductor layer on the first planar semiconductor layer. A first high concentration semiconductor layer is formed in a lower region of the first columnar semiconductor layer and in a region of the first planar semiconductor layer below the first columnar semiconductor layer. An insulating layer, a metal film, and a semiconductor film are sequentially formed on the first structure, and the semiconductor film, the metal film, and the insulating layer are sequentially etched with each leaving a sidewall shape on the sidewall on the first columnar semiconductor layer following etching. Another semiconductor film is then formed on the sidewall shape after etching the insulating film.Type: ApplicationFiled: June 24, 2016Publication date: October 20, 2016Inventors: Fujio MASUOKA, Hiroki NAKAMURA, Shintaro ARAI, Tomohiko KUDO, King-Jien CHUI, Yisuo LI, Yu JIANG, Xiang LI, Zhixian CHEN, Nansheng SHEN, Vladimir BLIZNETSOV, Kavitha Devi BUDDHARAJU, Navab SINGH
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Publication number: 20150357428Abstract: The semiconductor device according to the present invention is an nMOS SGT and is composed of a first n+ type silicon layer, a first gate electrode containing metal and a second n+ type silicon layer arranged on the surface of a first columnar silicon layer positioned vertically on a first planar silicon layer. Furthermore, a first insulating film is positioned between the first gate electrode and the first planar silicon layer, and a second insulating film is positioned on the top surface of the first gate electrode. In addition, the first gate electrode containing metal is surrounded by the first n+ type silicon layer, the second n+ type silicon layer, the first insulating film and the second insulating film.Type: ApplicationFiled: August 20, 2015Publication date: December 10, 2015Inventors: Fujio MASUOKA, Hiroki NAKAMURA, Shintaro ARAI, Tomohiko KUDO, King-Jien CHUI, Yisuo LI, Yu JIANG, Xiang LI, Zhixian CHEN, Nansheng SHEN, Vladimir BLIZNETSOV, Kavitha Devi BUDDHARAJU, Navab SINGH
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Patent number: 9153697Abstract: The semiconductor device according to the present invention is an nMOS SGT and is composed of a first n+ type silicon layer, a first gate electrode containing metal and a second n+ type silicon layer arranged on the surface of a first columnar silicon layer positioned vertically on a first planar silicon layer. Furthermore, a first insulating film is positioned between the first gate electrode and the first planar silicon layer, and a second insulating film is positioned on the top surface of the first gate electrode. In addition, the first gate electrode containing metal is surrounded by the first n+ type silicon layer, the second n+ type silicon layer, the first insulating film and the second insulating film.Type: GrantFiled: May 26, 2011Date of Patent: October 6, 2015Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE LTD.Inventors: Fujio Masuoka, Hiroki Nakamura, Shintaro Arai, Tomohiko Kudo, King-Jien Chui, Yisuo Li, Yu Jiang, Xiang Li, Zhixian Chen, Nansheng Shen, Vladimir Bliznetsov, Kavitha Devi Buddharaju, Navab Singh
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Patent number: 8735750Abstract: Embodiments provide a switching device. The switching device includes a substrate, which includes a contact region. The switching device further includes a vertical layer arrangement extending from the substrate next to the contact region. The vertical layer arrangement includes a control layer. The switching device further includes a freestanding silicon cantilever extending vertically from the contact region.Type: GrantFiled: November 3, 2011Date of Patent: May 27, 2014Assignee: Agency for Science, Technology and ResearchInventors: Jiaqiang Eldwin Ng, Ming Lin Julius Tsai, Navab Singh, Nansheng Shen
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Patent number: 8609494Abstract: The semiconductor device includes: a columnar silicon layer on the planar silicon layer; a first n+ type silicon layer formed in a bottom area of the columnar silicon layer; a second n+ type silicon layer formed in an upper region of the columnar silicon layer; a gate insulating film formed in a perimeter of a channel region between the first and second n+ type silicon layers; a gate electrode formed in a perimeter of the gate insulating film, and having a first metal-silicon compound layer; an insulating film formed between the gate electrode and the planar silicon layer, an insulating film sidewall formed in an upper sidewall of the columnar silicon layer; a second metal-silicon compound layer formed in the planar silicon layer; and an electric contact formed on the second n+ type silicon layer.Type: GrantFiled: May 16, 2013Date of Patent: December 17, 2013Assignee: Unisantis Electronics Singapore Pte Ltd.Inventors: Fujio Masuoka, Hiroki Nakamura, Shintaro Arai, Tomohiko Kudo, Yu Jiang, King-Jien Chui, Yisuo Li, Xiang Li, Zhixian Chen, Nansheng Shen, Vladimir Bliznetsov, Kavitha Devi Buddharaju, Navab Singh
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Patent number: 8563379Abstract: A method for producing a semiconductor device includes preparing a structure having a substrate, a planar semiconductor layer and a columnar semiconductor layer, forming a second drain/source region in the upper part of the columnar semiconductor layer, forming a contact stopper film and a contact interlayer film, and forming a contact layer on the second drain/source region. The step for forming the contact layer includes forming a pattern and etching the contact interlayer film to the contact stopper film using the pattern to form a contact hole for the contact layer and removing the contact stopper film remaining at the bottom of the contact hole by etching. The projection of the bottom surface of the contact hole onto the substrate is within the circumference of the projected profile of the contact stopper film formed on the top and side surface of the columnar semiconductor layer onto the substrate.Type: GrantFiled: December 10, 2012Date of Patent: October 22, 2013Assignee: Unisantis Electronics Singapore Pte Ltd.Inventors: Fujio Masuoka, Shintaro Arai, Hiroki Nakamura, Tomohiko Kudo, R. Ramana Murthy, Nansheng Shen, Kavitha Devi Buddharaju, Navab Singh
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Publication number: 20130252413Abstract: The semiconductor device includes: a columnar silicon layer on the planar silicon layer; a first n+ type silicon layer formed in a bottom area of the columnar silicon layer; a second n+ type silicon layer formed in an upper region of the columnar silicon layer; a gate insulating film formed in a perimeter of a channel region between the first and second n+ type silicon layers; a gate electrode formed in a perimeter of the gate insulating film, and having a first metal-silicon compound layer; an insulating film formed between the gate electrode and the planar silicon layer, an insulating film sidewall formed in an upper sidewall of the columnar silicon layer; a second metal-silicon compound layer formed in the planar silicon layer; and an electric contact formed on the second n+ type silicon layer.Type: ApplicationFiled: May 16, 2013Publication date: September 26, 2013Applicant: Unisantis Eletronics Singapore Pte.Ltd.Inventors: Fujio MASUOKA, Hiroki Nakamura, Shintaro Arai, Tomohiko Kudo, Yu Jiang, King-Jien Chui, Yisuo Li, Xiang Li, Zhixian Chen, Nansheng Shen, Vladimir Bliznetsov, Kavitha Devi Buddharaju, Navab Singh
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Patent number: 8486785Abstract: The semiconductor device includes: a columnar silicon layer on the planar silicon layer; a first n+ type silicon layer formed in a bottom area of the columnar silicon layer; a second n+ type silicon layer formed in an upper region of the columnar silicon layer; a gate insulating film formed in a perimeter of a channel region between the first and second n+ type silicon layers; a gate electrode formed in a perimeter of the gate insulating film, and having a first metal-silicon compound layer; an insulating film formed between the gate electrode and the planar silicon layer, an insulating film sidewall formed in an upper sidewall of the columnar silicon layer; a second metal-silicon compound layer formed in the planar silicon layer; and an electric contact formed on the second n+ type silicon layer.Type: GrantFiled: May 23, 2011Date of Patent: July 16, 2013Assignee: Unisantis Electronics Singapore Pte Ltd.Inventors: Fujio Masuoka, Hiroki Nakamura, Shintaro Arai, Tomohiko Kudo, Yu Jiang, King-Jien Chui, Yisuo Li, Xiang Li, Zhixian Chen, Nansheng Shen, Vladimir Bliznetsov, Kavitha Devi Buddharaju, Navab Singh
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Patent number: 8466512Abstract: A method for producing a semiconductor device includes preparing a structure having a substrate, a planar semiconductor layer and a columnar semiconductor layer, forming a second drain/source region in the upper part of the columnar semiconductor layer, forming a contact stopper film and a contact interlayer film, and forming a contact layer on the second drain/source region. The step for forming the contact layer includes forming a pattern and etching the contact interlayer film to the contact stopper film using the pattern to form a contact hole for the contact layer and removing the contact stopper film remaining at the bottom of the contact hole by etching. The projection of the bottom surface of the contact hole onto the substrate is within the circumference of the projected profile of the contact stopper film formed on the top and side surface of the columnar semiconductor layer onto the substrate.Type: GrantFiled: August 18, 2010Date of Patent: June 18, 2013Assignee: Unisantis Electronics Singapore Pte Ltd.Inventors: Fujio Masuoka, Shintaro Arai, Hiroki Nakamura, Tomohiko Kudo, R. Ramana Murthy, Nansheng Shen, Kavitha Devi Buddharaju, Navab Singh
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Publication number: 20120138437Abstract: Embodiments provide a switching device. The switching device includes a substrate, which includes a contact region. The switching device further includes a vertical layer arrangement extending from the substrate next to the contact region. The vertical layer arrangement includes a control layer. The switching device further includes a freestanding silicon cantilever extending vertically from the contact region.Type: ApplicationFiled: November 3, 2011Publication date: June 7, 2012Inventors: Jiaqiang Eldwin Ng, Ming Lin Julius Tsai, Navab Singh, Nansheng Shen
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Publication number: 20110303985Abstract: The semiconductor device includes: a columnar silicon layer on the planar silicon layer; a first n+ type silicon layer formed in a bottom area of the columnar silicon layer; a second n+ type silicon layer formed in an upper region of the columnar silicon layer; a gate insulating film formed in a perimeter of a channel region between the first and second n+ type silicon layers; a gate electrode formed in a perimeter of the gate insulating film, and having a first metal-silicon compound layer; an insulating film formed between the gate electrode and the planar silicon layer, an insulating film sidewall formed in an upper sidewall of the columnar silicon layer; a second metal-silicon compound layer formed in the planar silicon layer; and an electric contact formed on the second n+ type silicon layer.Type: ApplicationFiled: May 23, 2011Publication date: December 15, 2011Inventors: Fujio Masuoka, Hiroki Nakamura, Shintaro Arai, Tomohiko Kudo, Yu Jiang, King-Jien Chui, Yisuo Li, Xiang Li, Zhixian Chen, Nansheng Shen, Vladimir Bliznetsov, Kavitha Devi Buddharaju, Navab Singh
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Publication number: 20110303973Abstract: The semiconductor device according to the present invention is an nMOS SGT and is composed of a first n+ type silicon layer, a first gate electrode containing metal and a second n+ type silicon layer arranged on the surface of a first columnar silicon layer positioned vertically on a first planar silicon layer. Furthermore, a first insulating film is positioned between the first gate electrode and the first planar silicon layer, and a second insulating film is positioned on the top surface of the first gate electrode. In addition, the first gate electrode containing metal is surrounded by the first n+ type silicon layer, the second n+ type silicon layer, the first insulating film and the second insulating film.Type: ApplicationFiled: May 26, 2011Publication date: December 15, 2011Inventors: Fujio Masuoka, Hiroki Nakamura, Shintaro Arai, Tomohiko Kudo, King-Jien Chui, Yisuo Li, Yu Jiang, Xiang Li, Zhixian Chen, Nansheng Shen, Vladimir Bliznetsov, Kavitha Devi Buddharaju, Navab Singh
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Publication number: 20110042740Abstract: A method for producing a semiconductor device includes preparing a structure having a substrate, a planar semiconductor layer and a columnar semiconductor layer, forming a second drain/source region in the upper part of the columnar semiconductor layer, forming a contact stopper film and a contact interlayer film, and forming a contact layer on the second drain/source region. The step for forming the contact layer includes forming a pattern and etching the contact interlayer film to the contact stopper film using the pattern to form a contact hole for the contact layer and removing the contact stopper film remaining at the bottom of the contact hole by etching. The projection of the bottom surface of the contact hole onto the substrate is within the circumference of the projected profile of the contact stopper film formed on the top and side surface of the columnar semiconductor layer onto the substrate.Type: ApplicationFiled: August 18, 2010Publication date: February 24, 2011Applicant: UNISANTIS ELECTRONICS (JAPAN) LTD.Inventors: Fujio MASUOKA, Shintaro ARAI, Hiroki NAKAMURA, Tomohiko KUDO, R. Ramana MURTHY, Nansheng SHEN, Kavitha Devi BUDDHARAJU, Navab SINGH