Patents by Inventor Nanyan Wang

Nanyan Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10728063
    Abstract: In a PAM-N receiver, sampler reference levels, DC offset and AFE gain may be jointly adapted to achieve optimal or near-optimal boundaries for the symbol decisions of the PAM-N signal. For reference level adaptation, the hamming distances between two consecutive data samples and their in-between edge sample are evaluated. Reference levels for symbol decisions are adjusted accordingly such that on a data transition, an edge sample has on average, equal hamming distance to its adjacent data samples. DC offset may be compensated to ensure detectable data transitions for reference level adaptation. AFE gains may be jointly adapted with sampler reference levels such that the difference between a reference level and a pre-determined target voltage is minimized.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: July 28, 2020
    Assignee: Rambus Inc.
    Inventor: Nanyan Wang
  • Publication number: 20200145262
    Abstract: In a PAM-N receiver, sampler reference levels, DC offset and AFE gain may be jointly adapted to achieve optimal or near-optimal boundaries for the symbol decisions of the PAM-N signal. For reference level adaptation, the hamming distances between two consecutive data samples and their in-between edge sample are evaluated. Reference levels for symbol decisions are adjusted accordingly such that on a data transition, an edge sample has on average, equal hamming distance to its adjacent data samples. DC offset may be compensated to ensure detectable data transitions for reference level adaptation. AFE gains may be jointly adapted with sampler reference levels such that the difference between a reference level and a pre-determined target voltage is minimized.
    Type: Application
    Filed: October 4, 2019
    Publication date: May 7, 2020
    Inventor: Nanyan Wang
  • Patent number: 10461969
    Abstract: In a PAM-N receiver, sampler reference levels, DC offset and AFE gain may be jointly adapted to achieve optimal or near-optimal boundaries for the symbol decisions of the PAM-N signal. For reference level adaptation, the hamming distances between two consecutive data samples and their in-between edge sample are evaluated. Reference levels for symbol decisions are adjusted accordingly such that on a data transition, an edge sample has on average, equal hamming distance to its adjacent data samples. DC offset may be compensated to ensure detectable data transitions for reference level adaptation. AFE gains may be jointly adapted with sampler reference levels such that the difference between a reference level and a pre-determined target voltage is minimized.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: October 29, 2019
    Assignee: Rambus Inc.
    Inventor: Nanyan Wang
  • Patent number: 10411924
    Abstract: Methods and systems are provided for gain control in circuits. Gain applied in a circuit may be set to a baseline set gain. A first baseline parameter, associated with a first feature of a particular pattern of a signal at said baseline set gain, and a second baseline parameter, associated with a second feature of said particular pattern of the signal at said baseline set gain, may be determined. The gain is then set a current set gain, and a gain compression ratio may be determined based on one or more of said first baseline parameter, said second baseline parameter, a first current parameter associated with said first feature of at said current set gain, and a second current parameter associated with said second feature at said current set gain. Said current set gain may then be adjusted until said gain compression ratio reaches a predefined limit.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: September 10, 2019
    Assignee: MAXLINEAR ASIA SINGAPORE PTE LTD.
    Inventors: Nanyan Wang, Timothy Lupick
  • Publication number: 20180287831
    Abstract: In a PAM-N receiver, sampler reference levels, DC offset and AFE gain may be jointly adapted to achieve optimal or near-optimal boundaries for the symbol decisions of the PAM-N signal. For reference level adaptation, the hamming distances between two consecutive data samples and their in-between edge sample are evaluated. Reference levels for symbol decisions are adjusted accordingly such that on a data transition, an edge sample has on average, equal hamming distance to its adjacent data samples. DC offset may be compensated to ensure detectable data transitions for reference level adaptation. AFE gains may be jointly adapted with sampler reference levels such that the difference between a reference level and a pre-determined target voltage is minimized.
    Type: Application
    Filed: April 19, 2018
    Publication date: October 4, 2018
    Inventor: Nanyan Wang
  • Patent number: 9979571
    Abstract: In a PAM-N receiver, sampler reference levels, DC offset and AFE gain may be jointly adapted to achieve optimal or near-optimal boundaries for the symbol decisions of the PAM-N signal. For reference level adaptation, the hamming distances between two consecutive data samples and their in-between edge sample are evaluated. Reference levels for symbol decisions are adjusted accordingly such that on a data transition, an edge sample has on average, equal hamming distance to its adjacent data samples. DC offset may be compensated to ensure detectable data transitions for reference level adaptation.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: May 22, 2018
    Assignee: Rambus Inc.
    Inventor: Nanyan Wang
  • Publication number: 20170264470
    Abstract: In a PAM-N receiver, sampler reference levels, DC offset and AFE gain may be jointly adapted to achieve optimal or near-optimal boundaries for the symbol decisions of the PAM-N signal. For reference level adaptation, the hamming distances between two consecutive data samples and their in-between edge sample are evaluated. Reference levels for symbol decisions are adjusted accordingly such that on a data transition, an edge sample has on average, equal hamming distance to its adjacent data samples. DC offset may be compensated to ensure detectable data transitions for reference level adaptation.
    Type: Application
    Filed: November 30, 2015
    Publication date: September 14, 2017
    Inventor: Nanyan Wang
  • Publication number: 20170207937
    Abstract: Methods and systems are provided for gain control in circuits. Gain applied in a circuit may be set to a baseline set gain. A first baseline parameter, associated with a first feature of a particular pattern of a signal at said baseline set gain, and a second baseline parameter, associated with a second feature of said particular pattern of the signal at said baseline set gain, may be determined. The gain is then set a current set gain, and a gain compression ratio may be determined based on one or more of said first baseline parameter, said second baseline parameter, a first current parameter associated with said first feature of at said current set gain, and a second current parameter associated with said second feature at said current set gain. Said current set gain may then be adjusted until said gain compression ratio reaches a predefined limit.
    Type: Application
    Filed: February 28, 2017
    Publication date: July 20, 2017
    Inventors: Nanyan Wang, Timothy Lupick
  • Patent number: 9582018
    Abstract: An analog front-end (AFE) circuit has at least one AFE stage to generate a conditioned analog signal, and a gain control block to set a gain of the AFE stages. A finite state machine (FSM) block sets the gain to a baseline set gain without gain compression, or a current set gain with gain compression. An amplitude block determines amplitudes of the inner and outer eyes of a signal eye of the conditioned analog signal at the baseline set gain and the current set gain. A compression calculation block determines a gain compression of the conditioned analog signal at the current signal gain based on the relative changes in the respective amplitudes of the inner and outer signal eyes between the baseline and current set gains. The FSM block increases the current set gain until the gain compression ratio reaches a predefined limit.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: February 28, 2017
    Assignee: MAXLINEAR ASIA SINGAPORE PTE LTD.
    Inventors: Nanyan Wang, Timothy Lupick
  • Patent number: 9091711
    Abstract: A method and system are disclosed which determine a frequency offset between a reference clock frequency of a receiver and a transmit clock frequency embedded in a received non-return to zero (NRZ) signal. A polarity of the frequency offset is determined based on a moving direction of a sampling clock edge relative to an edge of a signal eye of the received NRZ signal and a region of the signal eye containing the sampling clock edge. A magnitude of the frequency offset is determined based on a time taken by the sampling clock edge to sweep the signal eye.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: July 28, 2015
    Assignee: PMC-Sierra US, Inc.
    Inventor: Nanyan Wang
  • Patent number: 8699558
    Abstract: This invention discloses circuit and methods to decouple and pipeline block decision feedback multiplexer (MUX) loop in parallel processing decision feedback circuits. In one embodiment of this invention, a block decision feedback MUX loop consists of a pipelined intra-block decision feedback MUX stage and an inter-block decision feedback MUX stage to handle intra-block decision feedback selection and inter-block decision feedback selection separately. In the pipelined intra-block decision feedback stage, inter-block dependency is eliminated to enable pipelining. In another embodiment of this invention for moderately timing-critical parallel processing decision feedback circuits, a block decision feedback MUX loop is piecewise split into multiple series connected segments that each segment contains parallel branches. The intra-segment decision feedback selections of different segments are decoupled and processed in parallel.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: April 15, 2014
    Assignee: PMC-Sierra US, Inc.
    Inventor: Nanyan Wang
  • Patent number: 8670512
    Abstract: Circuit and methods accelerate jitter tracking and reduce or eliminate the processing delay of loop filtering in timing recovery. A timing recovery circuit incorporates a phase tracking accelerator and a frequency tracking accelerator to compute the phase and frequency variation of incoming signal during the delay period of a loop filter. In one embodiment, phase and frequency tracking accelerators are realized in direct forms. In another embodiment, pre-computed look-up tables are employed in phase and frequency tracking accelerators to ease timing closure and simplify accelerator circuit. The phase tracking accelerator and the frequency tracking accelerator together compensate the estimated phase at the output of a loop filter and eliminate the processing delay of loop filtering. The loop bandwidth and jitter tolerance of timing recovery are increased.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: March 11, 2014
    Assignee: PMC-Sierra US, Inc.
    Inventor: Nanyan Wang
  • Patent number: 7714643
    Abstract: Apparatus and methods tune analog filters that are parts of systems. When an analog filter is inserted into a system, the analog filter can be difficult to tune because of the difficulty in observing the analog filter's characteristics without being interfered by other circuits in the system. In one embodiment, analog filters are bypassed, and a response is determined. To this response, a time-invariant digital filter is applied to generate a reference response, such as an ideal response. The analog filters are then enabled and adjusted so that the difference between the response of the system and the reference response is minimized. This technique can be applied to arbitrary-order analog filters and can be used even when other circuits affect the observed filter response.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: May 11, 2010
    Assignee: PMC-Sierra, Inc.
    Inventors: Nanyan Wang, Soon Sun Shin