Patents by Inventor Nao MATSUOKA

Nao MATSUOKA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230173027
    Abstract: A pharmaceutical composition containing the substance according to any one of the following (a) to (c), an organic acid, a metal salt of an organic acid, and a sugar and/or a sugar alcohol, wherein when the pharmaceutical composition is dissolved in distilled water for injection, a pH of the pharmaceutical composition is 3.0 to 4.
    Type: Application
    Filed: April 19, 2021
    Publication date: June 8, 2023
    Applicants: Shionogi & Co., Ltd., StemRim Inc.
    Inventors: Nao MATSUOKA, Shuichi HATANO, Yuya KUGA, Maki OKABE, Takehiko YAMAZAKI, Koichi YOKOTA
  • Patent number: 9949982
    Abstract: The present invention relates to a stable pharmaceutical composition comprising a compound represented by formula (I), its pharmaceutically acceptable salt or a solvate thereof. The stable pharmaceutical composition can be prepared by comprising 1) a compound represented by formula (I), its pharmaceutically acceptable salt, or a solvate thereof, 2) one or more selected from the group consisting of alkali metal chlorides, alkaline earth metal chlorides, transition metal chlorides and magnesium chloride; and 3) sugar and/or a sugar alcohol.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: April 24, 2018
    Assignee: Shionogi & Co., Ltd.
    Inventors: Hidenori Kawasaki, Natsuko Kojima, Atsushi Fujihira, Kanako Takahashi, Fumihiko Matsubara, Nao Matsuoka
  • Patent number: 9818467
    Abstract: According to one embodiment, a semiconductor memory device includes: a first bit line; a first source line; a first word line; a first control line; a first memory cell comprising a first variable resistance element and a first transistor, the first transistor including a gate coupled to the first word line, the first memory cell including one end coupled to the first bit line and another end coupled to the first source line; a second transistor including one end coupled to the first bit line; and a third transistor including a gate coupled to the first control line, one end coupled to the first bit line, and another end coupled to the first source line.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: November 14, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Nao Matsuoka, Kosuke Hatsuda, Katsuhiko Hoya
  • Publication number: 20170281639
    Abstract: The present invention relates to a stable pharmaceutical composition comprising a compound represented by formula (I), its pharmaceutically acceptable salt or a solvate thereof. The stable pharmaceutical composition can be prepared by comprising 1) a compound represented by formula (I), its pharmaceutically acceptable salt, or a solvate thereof, 2) one or more selected from the group consisting of alkali metal chlorides, alkaline earth metal chlorides, transition metal chlorides and magnesium chloride; and 3) sugar and/or a sugar alcohol.
    Type: Application
    Filed: September 3, 2015
    Publication date: October 5, 2017
    Inventors: Hidenori KAWASAKI, Natsuko KOJIMA, Atsushi FUJIHIRA, Kanako TAKAHASHI, Fumihiko MATSUBARA, Nao MATSUOKA
  • Publication number: 20170263297
    Abstract: According to one embodiment, a semiconductor memory device includes: a first bit line; a first source line; a first word line; a first control line; a first memory cell comprising a first variable resistance element and a first transistor, the first transistor including a gate coupled to the first word line, the first memory cell including one end coupled to the first bit line and another end coupled to the first source line; a second transistor including one end coupled to the first bit line; and a third transistor including a gate coupled to the first control line, one end coupled to the first bit line, and another and coupled to the first source line.
    Type: Application
    Filed: September 13, 2016
    Publication date: September 14, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Nao MATSUOKA, Kosuke HATSUDA, Katsuhiko HOYA
  • Publication number: 20160064073
    Abstract: A resistance change type memory device according to an embodiment includes a plurality of memory elements; a first to a fourth bit lines connected to the plurality of memory elements, respectively; a first to a fourth transistors connected at their one ends to the first to the fourth bit lines, respectively; a fifth transistor connected at its one end to the other ends of the first and second transistors; a sixth transistor connected at its one end to the other ends of the third and fourth transistors; and a fifth bit line connected to the other ends of the fifth and sixth transistors.
    Type: Application
    Filed: December 23, 2014
    Publication date: March 3, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Nao MATSUOKA, Kosuke HATSUDA, Mariko IIZUKA, Katsuhiko HOYA, Hiroyuki TAKENAKA