Abstract: Provided is a transmission drive circuit which can reduce distortions of a transmission signal and transmission noise, and is isolable from a signal line. A transmission drive circuit 700 includes a drive transistor 10 and an isolation diode 31 connected between a node n1 coupled to a signal line SL commonly used to propagate a transmission signal and a reception signal and a power source line HVP, and further includes an isolation diode 32 and a drive transistor 20 connected between the node n1 and a voltage line HVM. Furthermore, the transmission drive circuit 700 includes a switch 41 connected between a node n2 between the drive transistor 10 and the isolation diode 31, and a node n4 of a ground voltage Vs, and a switch 43 connected between a node n3 between the drive transistor 20 and the isolation diode 32, and a node n4.

Abstract: Provided is a transmission drive circuit which can reduce distortions of a transmission signal and transmission noise, and is isolable from a signal line. A transmission drive circuit 700 includes a drive transistor 10 and an isolation diode 31 connected between a node n1 coupled to a signal line SL commonly used to propagate a transmission signal and a reception signal and a power source line HVP, and further includes an isolation diode 32 and a drive transistor 20 connected between the node n1 and a voltage line HVM. Furthermore, the transmission drive circuit 700 includes a switch 41 connected between a node n2 between the drive transistor 10 and the isolation diode 31, and a node n4 of a ground voltage Vs, and a switch 43 connected between a node n3 between the drive transistor 20 and the isolation diode 32, and a node n4.

Abstract: When a high-voltage output is Hi, a first N-type transistor and a second P-type transistor are in an OFF state, and a second N-type transistor and a first P-type transistor are in an ON state, where a high voltage is applied to drain-source of the first N-type transistor. In a process to shift the high voltage output to Lo, a gate potential of the first N-type transistor is once put to an intermediate state between VDD and GND to lower a drain-source voltage of the first N-type transistor, then the gate potential is raised to VDD. In this manner, a state where the drain-source voltage of the first N-type transistor is large and also a drain current of the same is large is avoided, so that an On withstand voltage of the level shift circuit is increased, thereby preventing a breakdown.

Abstract: A level shift 9, IGBT1, 2 and a AND element 10 are provided. An output DOUT is controlled to four states Hi/Lo/HiZ/artificial Hi by controlling input signals IN1, IN2, IN3, PULSE_IN. An element is protected from output short circuiting by transferring an output after a fixed time period to an artificial Hi. Furthermore NMOS are connected in parallel between two inverter circuits and the two stage of the inverter circuit is connected to the gate of NMOS. A delay circuit connecting the output of the initial state of the inverter circuit to a drain and the source of the NMOS to GND is connected to PULSE_IN of the level shift 9. Thus it is possible to almost completely eliminate temperature dependency of the delay time.

Abstract: The present invention provides a semiconductor integrated-circuit device capable of achieving higher-density integration and faster operation, and a CMOS circuit operational speeding-up method for easily achieving the operating speeds of CMOS circuits, including existing one. A signal transferring path includes a plurality of CMOS-constructed logic gate circuits provided between one pair of flip-flop circuits for acquiring and holding signals by use of clock signals. The signal transferring path includes a first and a second signal transferring path. The first signal transferring path is constituted by enhancement-type MOSFETs and has a signal transferring delay time equal to, or less than, a permissible signal transferring delay time.

Abstract: The present invention provides a semiconductor integrated-circuit device capable of achieving higher-density integration and faster operation, and a CMOS circuit operational speeding-up method for easily achieving the operating speeds of CMOS circuits, including existing one.