Patents by Inventor Nao OTSUKA
Nao OTSUKA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10503197Abstract: A current generation circuit includes: a current source circuit including a first transistor and a first resistor, and configured to output a first current based on a source voltage or a drain voltage of the first transistor and a resistance of the first resistor; a current control circuit including a voltage input terminal, a second transistor and a third transistor, and configured to output a second current based on a source voltage of the second transistor and a resistance of the third transistor; and an impedance circuit including a second resistor formed of a same resistive body as the first resistor and a fourth transistor diode-connected to the second resistor, and configured to generate a control voltage at the voltage input terminal by the first current and the second current, wherein the current generation circuit is configured to output a current based on the second current.Type: GrantFiled: December 14, 2018Date of Patent: December 10, 2019Assignee: ABLIC INC.Inventors: Masakazu Sugiura, Atsushi Igarashi, Nao Otsuka
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Publication number: 20190187739Abstract: A current generation circuit includes: a current source circuit including a first transistor and a first resistor, and configured to output a first current based on a source voltage or a drain voltage of the first transistor and a resistance of the first resistor; a current control circuit including a voltage input terminal, a second transistor and a third transistor, and configured to output a second current based on a source voltage of the second transistor and a resistance of the third transistor; and an impedance circuit including a second resistor formed of a same resistive body as the first resistor and a fourth transistor diode-connected to the second resistor, and configured to generate a control voltage at the voltage input terminal by the first current and the second current, wherein the current generation circuit is configured to output a current based on the second current.Type: ApplicationFiled: December 14, 2018Publication date: June 20, 2019Inventors: Masakazu SUGIURA, Atsushi IGARASHI, Nao OTSUKA
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Patent number: 10288694Abstract: A secondary battery monitoring device is equipped with a resistance circuit and a detection circuit detecting an abnormality of a secondary battery, a current generation circuit generating a failure detection circuit for setting an output terminal of the resistance circuit to a failure diagnosis voltage, and a switch which permits the failure detection circuit to flow to the output terminal of the resistance circuit by switching. Further, a method for diagnosing failure of the secondary battery monitoring device is provided.Type: GrantFiled: December 14, 2017Date of Patent: May 14, 2019Assignee: ABLIC INC.Inventors: Yasuhiro Miyamoto, Nao Otsuka, Atsushi Igarashi
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Publication number: 20180172771Abstract: A secondary battery monitoring device is equipped with a resistance circuit and a detection circuit detecting an abnormality of a secondary battery, a current generation circuit generating a failure detection circuit for setting an output terminal of the resistance circuit to a failure diagnosis voltage, and a switch which permits the failure detection circuit to flow to the output terminal of the resistance circuit by switching. Further, a method for diagnosing failure of the secondary battery monitoring device is provided.Type: ApplicationFiled: December 14, 2017Publication date: June 21, 2018Inventors: Yasuhiro MIYAMOTO, Nao OTSUKA, Atsushi IGARASHI
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Patent number: 9983067Abstract: Provided is an overheat detection circuit configured to accurately detect a temperature of a semiconductor device even at high temperature and thus avoid outputting an erroneous detection result. The overheat detection circuit includes: a PN junction element, being a temperature sensitive element; a constant current circuit configured to supply the PN junction element with a bias current; a comparator configured to compare a voltage generated at the PN junction element and a reference voltage; a second PN junction element configured to cause a leakage current to flow through a reference voltage circuit at high temperature; and a third PN junction element configured to bypass a leakage current of the constant current circuit at the high temperature.Type: GrantFiled: April 22, 2015Date of Patent: May 29, 2018Assignee: ABLIC INC.Inventors: Masakazu Sugiura, Tsutomu Tomioka, Hideyuki Sawai, Atsushi Igarashi, Nao Otsuka, Daisuke Okano
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Patent number: 9733284Abstract: To provide a current detection circuit capable of suppressing the occurrence of a large potential difference between input terminals of a differential amplifier circuit, and preventing degradation of input transistors. A differential amplifier circuit is equipped with a clamp circuit which limits gate-source voltages of a pair of PMOS transistors each having a bulk and a source connected to each other with the sources of the pair of PMOS transistors as input terminals.Type: GrantFiled: April 5, 2016Date of Patent: August 15, 2017Assignee: SII SEMICONDUCTOR CORPORATIONInventors: Atsushi Igarashi, Nao Otsuka, Masakazu Sugiura
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Publication number: 20160305985Abstract: To provide a current detection circuit capable of suppressing the occurrence of a large potential difference between input terminals of a differential amplifier circuit, and preventing degradation of input transistors. A differential amplifier circuit is equipped with a clamp circuit which limits gate-source voltages of a pair of PMOS transistors each having a bulk and a source connected to each other with the sources of the pair of PMOS transistors as input terminals.Type: ApplicationFiled: April 5, 2016Publication date: October 20, 2016Inventors: Atsushi IGARASHI, Nao OTSUKA, Masakazu SUGIURA
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Patent number: 9454174Abstract: Provided is a power supply voltage monitoring circuit capable of accurately detecting a power supply voltage with a small circuit scale and low power consumption. The power supply voltage monitoring circuit includes: a signal output circuit configured to output a signal voltage representing saturation characteristics with respect to an increase in power supply voltage; and a signal voltage monitoring circuit configured to output a signal representing that the signal voltage of the signal output circuit is normal, the signal voltage monitoring circuit including: a PMOS transistor including a gate connected to an output terminal of the signal output circuit; a first constant current circuit connected to a drain of the PMOS transistor; and an inverter including an input terminal connected to the drain of the PMOS transistor.Type: GrantFiled: April 22, 2015Date of Patent: September 27, 2016Assignee: SII SEMICONDUCTOR CORPORATIONInventors: Atsushi Igarashi, Nao Otsuka
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Publication number: 20160064916Abstract: Provided is a semiconductor device including a detection circuit in which, even when a load short-circuit detection circuit and a load open-circuit detection circuit perform false detection due to a fluctuation in power supply voltage and the like, an output of a false detection result can be prevented. The detection circuit includes the load short-circuit detection circuit configured to detect a short circuit of a load, the load open-circuit detection circuit configured to detect an open circuit of the load, and a logic circuit configured to output output signals of the load short-circuit detection circuit and the load open-circuit detection circuit to an output terminal of the logic circuit, in which the logic circuit outputs a signal of a non-detection logic to the output terminal when the outputs of the load open-circuit detection circuit and the load short-circuit detection circuit are detection logics.Type: ApplicationFiled: August 27, 2015Publication date: March 3, 2016Inventors: Masakazu SUGIURA, Atsushi IGARASHI, Nao OTSUKA
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Publication number: 20150309528Abstract: Provided is a power supply voltage monitoring circuit capable of accurately detecting a power supply voltage with a small circuit scale and low power consumption. The power supply voltage monitoring circuit includes: a signal output circuit configured to output a signal voltage representing saturation characteristics with respect to an increase in power supply voltage; and a signal voltage monitoring circuit configured to output a signal representing that the signal voltage of the signal output circuit is normal, the signal voltage monitoring circuit including: a PMOS transistor including a gate connected to an output terminal of the signal output circuit; a first constant current circuit connected to a drain of the PMOS transistor; and an inverter including an input terminal connected to the drain of the PMOS transistor.Type: ApplicationFiled: April 22, 2015Publication date: October 29, 2015Inventors: Atsushi IGARASHI, Nao OTSUKA
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Publication number: 20150308902Abstract: Provided is an overheat detection circuit configured to accurately detect a temperature of a semiconductor device even at high temperature and thus avoid outputting an erroneous detection result. The overheat detection circuit includes: a PN junction element, being a temperature sensitive element; a constant current circuit configured to supply the PN junction element with a bias current; a comparator configured to compare a voltage generated at the PN junction element and a reference voltage; a second PN junction element configured to cause a leakage current to flow through a reference voltage circuit at high temperature; and a third PN junction element configured to bypass a leakage current of the constant current circuit at the high temperature.Type: ApplicationFiled: April 22, 2015Publication date: October 29, 2015Inventors: Masakazu SUGIURA, Tsutomu TOMIOKA, Hideyuki SAWAI, Atsushi IGARASHI, Nao OTSUKA, Daisuke OKANO
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Patent number: 8829885Abstract: Provided is a voltage reference circuit which is able to obtain high PSRR without a variation in power-supply voltage and an influence of noise. A voltage reference circuit for performing voltage-current conversion on forward voltages of PN junction elements and on a difference therebetween to generate a voltage so as not to depend on a temperature is constituted by an amplifier for controlling a temperature characteristic of a voltage of an output terminal, a source follower circuit for supplying a power to the amplifier, and a PMOS transistor which is controlled by the amplifier and which controls a current to flow into the PN junction elements.Type: GrantFiled: March 4, 2013Date of Patent: September 9, 2014Assignee: Seiko Instrumentals Inc.Inventors: Nao Otsuka, Kosuke Takada
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Publication number: 20130249525Abstract: Provided is a voltage reference circuit which is able to obtain high PSRR without a variation in power-supply voltage and an influence of noise. A voltage reference circuit for performing voltage-current conversion on forward voltages of PN junction elements and on a difference therebetween to generate a voltage so as not to depend on a temperature is constituted by an amplifier for controlling a temperature characteristic of a voltage of an output terminal, a source follower circuit for supplying a power to the amplifier, and a PMOS transistor which is controlled by the amplifier and which controls a current to flow into the PN junction elements.Type: ApplicationFiled: March 4, 2013Publication date: September 26, 2013Applicant: SEIKO INSTRUMENTS INC.Inventors: Nao OTSUKA, Kosuke TAKADA