Abstract: A circuit configuration is adopted which supplies an internal power supply voltage from outside and inside of a semiconductor chip 1. The internal power supply voltage from the outside is supplied through an internal power supply pad 20, whereas the internal power supply voltage from the inside is supplied through a regulator 110. The regulator 110 is arranged in an area giving a remarkable level reduction due to the voltage drop in an internal power supply wiring 21a, thereby supplementing shortage in the internal power supply voltage from the internal power supply pad 20.

Abstract: A four-input to two-output adder is disclosed. The four-input/two-output adder includes a sum-lookahead full adder and a modified full adder. The sum-lookahead full adder includes an XOR3 block and an AXOR block for receiving a first input, a second input, a third input, and an input from a forward adjacent adder to generate a first sum signal and a sum-lookahead carry signal, respectively. The modified full adder includes an XOR2 block and a MUX2 block for receiving the first sum signal from the sum-lookahead-full adder, a fourth input, and a sum-lookahead carry signal from a backward adjacent adder to generate a second sum signal and a carry signal, respectively.

Abstract: A system and method for ensuring comprehensive testing coverage of components within a dynamic logic macro during a burn-in test cycle. Burn-in testing is initiated within dynamic logic circuit having a dynamic logic block and a self-reset loop for generating a reset signal. A multiple phase burn-in test input is applied to the self-reset loop for modifying the duration of the reset signal during burn-in testing, such that the components within the dynamic logic macro are adequately stressed during the burn-in test cycle.

Abstract: A processor cycle time independent pipeline cache and method for pipelining data from a cache provide a processor with operand data and instructions without introducing additional latency for synchronization when processor frequency is lowered or when a reload port provides a value a cycle earlier than a read access from the cache storage. The cache incorporates a persistent data bus that synchronizes the stored data access with the pipeline and can also utilize bypass mode data available from a cache input from the lower level when data is being written to the cache.

Abstract: A set-associative cache memory having a built-in set prediction array is disclosed. The cache memory can be accessed via an effective address having a tag field, a line index field, and a byte field. The cache memory includes a directory, a memory array, a translation lookaside buffer, and a set prediction array. The memory array is associated with the directory such that each tag entry within the directory corresponds to a cache line within the memory array. In response to a cache access by an effective address, the translation lookaside buffer determines whether or not the data associated with the effective address is stored within the memory array. The set prediction array is built-in within the memory array such that an access to a line entry within the set prediction array can be performed in a same access cycle as an access to a cache line within the memory array.

Abstract: A true/complement signal generator for a dynamic logic circuit having a dynamic node is disclosed. The true/complement signal generator for a dynamic logic circuit having a dynamic node includes a cascaded inverter circuit, a first half-latch circuit, and a second half-latch circuit. The cascaded inverter circuit, which is connected to the dynamic node, includes a first inverter connected in series with a second inverter. Connected to an output of the second inverter of the cascaded inverter circuit, the first half-latch circuit generates an output signal. Connected to an output of the first inverter of the cascaded inverter circuit, the second half-latch circuit generates a complement output signal.

Abstract: A high-speed incrementer array for incrementing a data input value by a binary one, wherein the data input value comprises a plurality of input bit values. The incrementer array includes a plurality of word lines, bit-line pairs, and sense amplifiers. The input bit values are received as a plurality of complement input signals and a plurality of true input signals. The complement input signals are transmitted on the plurality of word lines that form the rows of the array. Each one of plurality of bit-line pairs is located in a respective column of the array and is coupled to particular ones of the word lines in the rows of the array. Each one of the plurality of sense amplifiers is coupled to a respective bit-line pair for sensing a voltage difference between the bit-line pair, such that the bit-line pair and the sense amplifier perform a logical NOR of the complement input signals to produce a NOR output.

Abstract: A high-speed rotator array for shifting input data a specified amount. The rotator array includes a plurality of straight shift control lines extending across the array for receiving shift data representative of shift values, and a plurality of input terminals for receiving input data to be shifted. The rotator array also includes a plurality of data lines coupled to the plurality of input terminals that extend both diagonally and horizontally across the array. In response to the rotator array receiving the shift data and the input data, a plurality of output terminals transmit the shifted output data.