Abstract: A semiconductor memory device includes a memory cell array, a storing unit that stores data read out from the memory cell array in storage circuits, an output circuit, and a control circuit. In response to a read request, the control circuit adjusts the value of a read pointer of the storing unit, controls the storing unit to sequentially output to the output circuit first and second data stored in first and second storage circuits of the storing unit, respectively, the read pointer having a first value that references the first storage circuit when the first data is output, and a second value that references the second storage circuit when the second data is output, and controls the output circuit to transmit the first and second data to the memory controller as dummy data, and thereafter to transmit at least third data to the memory controller as read data.

Abstract: A memory system includes a semiconductor storage device in an embodiment that performs transfer of a command, an address, and transfer data excluding the command and the address between a controller and a nonvolatile memory. The controller and the nonvolatile memory transfer the command and the address in synchronization with a capturing signal during writing and readout, transfer the transfer data in synchronization with a synchronous control signal, and transfer the command, the address, and the transfer data in synchronization with the capturing signal during function setting for the nonvolatile memory.

Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array; a conversion circuit; a data bus; a first buffer and a second buffer; and a third buffer. The data bus includes a first wiring part extending along a first direction. The first buffer and the second buffer are separate from each other. The first to third buffers are at different positions along the first direction.

Abstract: A memory system includes a semiconductor storage device in an embodiment that performs transfer of a command, an address, and transfer data excluding the command and the address between a controller and a nonvolatile memory. The controller and the nonvolatile memory transfer the command and the address in synchronization with a capturing signal during writing and readout, transfer the transfer data in synchronization with a synchronous control signal, and transfer the command, the address, and the transfer data in synchronization with the capturing signal during function setting for the nonvolatile memory.

Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array; a conversion circuit; a data bus; a first buffer and a second buffer; and a third buffer. The data bus includes a first wiring part extending along a first direction. The first buffer and the second buffer are separate from each other. The first to third buffers are at different positions along the first direction.

Abstract: A semiconductor device includes first, second and third semiconductor regions, each surrounded by an element isolation layer, first and second transistors of the first semiconductor region connected in parallel between first and second nodes, a third transistor of the second semiconductor region between the second node and the first transistor, and a fourth transistor of the third semiconductor region between the second node and the second transistor. Gates of the first and second transistors extend in a first direction and are spaced from each other in a second direction. A first distance which is equal to a longer of two distances between the element isolation layer and the gate electrode of the first transistor in the second direction, is greater than a second distance which is equal to a longer of two distances between the element isolation layer and the gate electrode of the third transistor in the second direction.

Abstract: A semiconductor device includes first, second and third semiconductor regions, each surrounded by an element isolation layer, first and second transistors of the first semiconductor region connected in parallel between first and second nodes, a third transistor of the second semiconductor region between the second node and the first transistor, and a fourth transistor of the third semiconductor region between the second node and the second transistor. Gates of the first and second transistors extend in a first direction and are spaced from each other in a second direction. A first distance which is equal to a longer of two distances between the element isolation layer and the gate electrode of the first transistor in the second direction, is greater than a second distance which is equal to a longer of two distances between the element isolation layer and the gate electrode of the third transistor in the second direction.

Abstract: According to one embodiment, a frequency divider circuit includes a 1st flip-flop including a 1st terminal to which a clock signal is input, and including a 2nd terminal to which a 1st signal is input; a 2nd flip-flop including a 1st terminal to which the clock signal is input, and including a 2nd terminal to which a 2nd signal is input, the 2nd signal being output from the 1st flip-flop; a 3rd flip-flop including a 1st terminal to which the clock signal is input, and including a 2nd terminal to which a 3rd signal is input, the 3rd signal being output from the 2nd flip-flop; and an exclusive OR gate including a 1st terminal to which the 4th signal is input, and including a 2nd terminal to which a 5th signal is input, the 5th signal being output from the 2nd flip-flop.

Abstract: According to one embodiment, a frequency divider circuit includes a 1st flip-flop including a 1st terminal to which a clock signal is input, and including a 2nd terminal to which a 1st signal is input; a 2nd flip-flop including a 1st terminal to which the clock signal is input, and including a 2nd terminal to which a 2nd signal is input, the 2nd signal being output from the 1st flip-flop; a 3rd flip-flop including a 1st terminal to which the clock signal is input, and including a 2nd terminal to which a 3rd signal is input, the 3rd signal being output from the 2nd flip-flop; and an exclusive OR gate including a 1st terminal to which the 4th signal is input, and including a 2nd terminal to which a 5th signal is input, the 5th signal being output from the 2nd flip-flop.

Abstract: A semiconductor device includes a first transistor connected to an internal voltage terminal and a first node at which a first resistance unit is connected. The first resistance unit includes a resistor connected between the first node and a node from which a monitoring voltage is provided for controlling the first transistor. This resistance unit also includes a first resistance adjustment unit connected in parallel with the first resistor. Also included is a second resistance unit having a third resistor connected between the monitor node and a second node which is connected to a ground potential and a second resistance adjustment unit connected in parallel with the third resistor. A comparator comparing the monitor node voltage to a reference is provided with an output terminal connected the first transistor. Also included is a control circuit to control the resistance adjustment units.

Abstract: A semiconductor memory device according to an embodiment is provided with a plurality of first latch circuits that latch setting-data at different timings, a plurality of hold circuits provided corresponding to the respective plurality of first latch circuits, each holding data latched by the corresponding first latch circuit, and an address decoder that decodes an address that specifies a destination to hold data. Each of the plurality of hold circuits has one or more holding parts that hold data latched by the corresponding first latch circuit based on a decode signal decoded by the address decoder.

Abstract: A semiconductor memory device according to an embodiment is provided with a plurality of first latch circuits that latch setting-data at different timings, a plurality of hold circuits provided corresponding to the respective plurality of first latch circuits, each holding data latched by the corresponding first latch circuit, and an address decoder that decodes an address that specifies a destination to hold data. Each of the plurality of hold circuits has one or more holding parts that hold data latched by the corresponding first latch circuit based on a decode signal decoded by the address decoder.

Abstract: A semiconductor device includes a first transistor connected to an internal voltage terminal and a first node at which a first resistance unit is connected. The first resistance unit includes a resistor connected between the first node and a node from which a monitoring voltage is provided for controlling the first transistor. This resistance unit also includes a first resistance adjustment unit connected in parallel with the first resistor. Also included is a second resistance unit having a third resistor connected between the monitor node and a second node which is connected to a ground potential and a second resistance adjustment unit connected in parallel with the third resistor. A comparator comparing the monitor node voltage to a reference is provided with an output terminal connected the first transistor. Also included is a control circuit to control the resistance adjustment units.

Abstract: Plural data lines read normal data stored in a first area in the memory cell array when the data lines are connected to a selected bit line. Plural parity data lines read parity data from a second area in the memory cell array different from the first area, the parity data being used for an error correction of the normal data stored in the memory cell. A first determination circuit compares the normal data read from the data lines and their expectation value, respectively, and determines whether the data and the expectation value coincide, respectively. A second determination circuit compares the parity data read from the parity data lines and their expectation value, respectively, and determines whether the data and the expectation value coincide, respectively. The second determination circuit includes a selection circuit that selectively outputs a determination result on a part of the parity data lines.

Abstract: A semiconductor device includes plural memory cell blocks, each having a memory array of plural memory cells. Plural control circuits are provided in correspondence with each of the memory cell blocks, for writing information to the memory cell blocks and for reading information written in the memory cell blocks. Plural input/output terminals are for inputting the information to be written and for outputting the information to be read. Plural multiplexers are provided in correspondence with each of the input/output terminals, for conveying the information to be written from the input/output terminals and for conveying the information to be read to the input/.output terminals. A bidirectional transfer type buffer is connected to each connection line between the control circuits and the multiplexers, for selectively conveying information from the control circuits to each of the multiplexers and for selectively conveying information from the multiplexers to each of the control circuits.

Abstract: A semiconductor device includes plural memory cell blocks, each having a memory cell array of plural memory cells. Plural control circuits are provided in correspondence with each of the memory cell blocks, for writing information to the memory cell blocks and for reading information written in the memory cell blocks. Plural input/output terminals are for inputting the information to be written and for outputting the information to be read. Plural multiplexers are provided in correspondence with each of the input/output terminals, for conveying the information to be written from the input/output terminals and for conveying the information to be read to the input/output terminals. A bidirectional transfer type buffer is connected to each connection line between the control circuits and the multiplexers, for selectively conveying information from the control circuits to each of the multiplexers and for selectively conveying information from the multiplexers to each of the control circuits.

Abstract: Plural data lines read normal data stored in a first area in the memory cell array when the data lines are connected to a selected bit line. Plural parity data lines read parity data from a second area in the memory cell array different from the first area, the parity data being used for an error correction of the normal data stored in the memory cell. A first determination circuit compares the normal data read from the data lines and their expectation value, respectively, and determines whether the data and the expectation value coincide, respectively. A second determination circuit compares the parity data read from the parity data lines and their expectation value, respectively, and determines whether the data and the expectation value coincide, respectively. The second determination circuit includes a selection circuit that selectively outputs a determination result on a part of the parity data lines.

Abstract: A semiconductor memory device adopting a bit line twist system in which at least a part of bit lines are twisted, includes memory cell arrays each having a plurality of memory cells to store data, redundancy cell arrays each having a plurality of redundancy cells to replace a defective cell in the memory cell array, and a control circuit which performs control to invert a direction of the data. The device further includes an inversion circuit which inverts the direction of the data, in accordance with the control by the control circuit.

Abstract: A semiconductor memory device adopting a bit line twist system in which at least a part of bit lines are twisted, includes memory cell arrays each having a plurality of memory cells to store data, redundancy cell arrays each having a plurality of redundancy cells to replace a defective cell in the memory cell array, and a control circuit which performs control to invert a direction of the data. The device further includes an inversion circuit which inverts the direction of the data, in accordance with the control by the control circuit.

Abstract: There is provided a semiconductor memory device of a overlaid-DQ system having a column redundancy technique having high efficiency of replacing a defective address without largely increasing a chip size. Regarding DRAM of the overlaid-DQ bus type, in a metal line layer formed at an upper portion than bit lines, 256 pairs of DQ lines (DQ0 to DQ255) are formed in a form to be overlaid on the memory cell array. Each of spare circuits (a spare column, its sense amplifier (S/A), a pair of spare DQ lines (pair of SDQ lines SDQ0 to SDQ3)) is arranged per 64 pairs of DQ lines. Four sets of spare circuits may be structured as a column redundancy in connection with the 256 pairs of DQ lines, each set of spare circuits may be structured in connection with 65 pairs of DQ lines.