Abstract: A semiconductor apparatus and a continuous readout method for improving prior continuous readout are provided. A flash memory includes: a NAND memory cell array, an input/output circuit, an ECC circuit, a controller, a word-line selection circuit, a page buffer/readout circuit, and a row selection circuit. When performing the continuous readout of pages, the controller performs an array readout of a first half page of a selection page on the memory cell array and an array readout of a second half page of the selection page on the memory cell array independently, and continuously outputs the respectively read data of the half pages in synchronization with a clock signal.

Abstract: A semiconductor memory device includes a memory cell array, a memory apparatus and a power-on operation apparatus, and is capable of knowing whether a reading of the setting information which is set during the power-on operation had been completed correctly or not. The flash memory reads the fuse memory when it is detected that the power supply has reached the power-on detection level, and determines whether the reading of the fuse memory had been completed correctly. When not completed correctly, the fuse memory is read again within the maximum read count, and the setting information (which was read from the fuse memory) is written into the CF register. The identification information (that identifies whether the reading of the fuse memory has been completed correctly or not) is stored in the register.

Abstract: A semiconductor device that can automatically transition from a standby mode to a deep power down (DPD) mode is provided. The semiconductor device includes a DPD controller supporting the DPD mode and multiple internal circuits. The DPD controller measures a time since a time point of entering the standby mode and generates multiple power down enable signals for further reducing power consumption in the standby mode in response to elapse of a measurement time, so that operations of the multiple internal circuits are stopped in stages.

Abstract: A semiconductor storing apparatus and a flash memory operation method, for shortening a recovery time from a deep power-down (DPD) mode without a dedicated command for the DPD are provided. A flash memory includes: a standard command interface circuit and a DPD controller, operating through an external power voltage; a voltage supply node, for supplying power from the external power voltage via a first current path; a voltage supply node, for supplying power from the external power voltage via a second current path; an internal circuit group, connected to the voltage supply node; and a charge pump circuit, connected to the voltage supply node. When the DPD mode is released, the internal circuit group is enabled after the charge pump circuit is enabled.

Abstract: A power down detection circuit that may detect a supply voltage decrease more accurately is provided. The power down detection circuit includes a BGR circuit generating a reference voltage VREF, a resistance division circuit generating a first internal voltage VCC_DIV1 and a second internal voltage VCC_DIV2 based on a supply voltage VCC, a first comparator outputting a reset signal PDDRST when detecting VCC_DIV1<VREF, a second comparator outputting a switching signal SEL when detecting VCC_DIV2<VREF, a charging pump circuit generating a boosted voltage VXX based on the supply voltage VCC, and a switching circuit switching an operating voltage supplied to the BGR circuit to the supply voltage VCC or the boosted voltage VXX based on the switching signal SEL.

Abstract: A semiconductor device capable of automatically transitioning from a standby mode to a deep power down (DPD) mode is provided. The semiconductor device includes: internal circuits capable of operating in response to an input signal from an input/output circuit; and a controller capable of controlling operations of the internal circuits. The internal circuit supporting the DPD mode includes: a measurement part, measuring a time since a time point of the semiconductor device entering the standby mode; a transition time detection part, detecting a case where a measurement time of the measurement part has reached a certain time; and a DPD signal generation part, generating a power down enable signal for further reducing power consumption in the standby mode when a transition time is detected.

Abstract: A semiconductor apparatus and a continuous readout method for improving prior continuous readout are provided. A flash memory includes: a NAND memory cell array, an input/output circuit, an ECC circuit, a controller, a word-line selection circuit, a page buffer/readout circuit, and a row selection circuit. When performing the continuous readout of pages, the controller performs an array readout of a first half page of a selection page on the memory cell array and an array readout of a second half page of the selection page on the memory cell array independently, and continuously outputs the respectively read data of the half pages in synchronization with a clock signal.

Abstract: A flash memory capable of automatically releasing a deep power-down mode is provided. The flash memory includes: a standard command interface (I/F) circuit and a deep power-down mode (DPD) controller, operating through an external power voltage; and an internal circuit, operating through internal voltages supplied from voltage supply nodes. The DPD controller detects whether the flash memory is in the deep power-down mode when a standard command is inputted to the standard command I/F circuit and recovers the internal circuit from the DPD mode in the case where the deep power-down mode is detected. The standard command is executed after the internal circuit is recovered.

Abstract: Providing a semiconductor memory device capable of knowing whether a reading of the setting information which is set during the power-on operation had been completed correctly or not. The flash memory in the present invention reads the fuse memory when it is detected that the power supply has reached the power-on detection level, and determines whether the reading of the fuse memory had been completed correctly. When not completed correctly, the fuse memory is read again within the maximum read count, and the setting information (which was read from the fuse memory) is written into the CF register. Furthermore, the identification information (that identifies whether the reading of the fuse memory has been completed correctly or not) is stored in the register.

Abstract: A power down detection circuit that may detect a supply voltage decrease more accurately is provided. The power down detection circuit includes a BGR circuit generating a reference voltage VREF, a resistance division circuit generating a first internal voltage VCC_DIV1 and a second internal voltage VCC_DIV2 based on a supply voltage VCC, a first comparator outputting a reset signal PDDRST when detecting VCC_DIV1<VREF, a second comparator outputting a switching signal SEL when detecting VCC_DIV2<VREF, a charging pump circuit generating a boosted voltage VXX based on the supply voltage VCC, and a switching circuit switching an operating voltage supplied to the BGR circuit to the supply voltage VCC or the boosted voltage VXX based on the switching signal SEL.

Abstract: A semiconductor storage apparatus capable of realizing continuous read with high speed is provided. A continuous read method of a NAND flash memory includes: a step for holding setting information related to a read time of a memory cell array in continuous read in a register; a step for reading data from the memory cell array in the read time based on the setting information; a step for holding the read data in a latch (L1) and a latch (L2); and a step for outputting the data held synchronously with an external clock signal corresponding to the setting information.

Abstract: A semiconductor storing apparatus and a flash memory operation method, for shortening a recovery time from a deep power-down (DPD) mode without a dedicated command for the DPD are provided. A flash memory includes: a standard command interface circuit and a DPD controller, operating through an external power voltage; a voltage supply node, for supplying power from the external power voltage via a first current path; a voltage supply node, for supplying power from the external power voltage via a second current path; an internal circuit group, connected to the voltage supply node; and a charge pump circuit, connected to the voltage supply node. When the DPD mode is released, the internal circuit group is enabled after the charge pump circuit is enabled.

Abstract: A flash memory capable of automatically releasing a deep power-down mode is provided. The flash memory includes: a standard command interface (I/F) circuit and a deep power-down mode (DPD) controller, operating through an external power voltage; and an internal circuit, operating through internal voltages supplied from voltage supply nodes. The DPD controller detects whether the flash memory is in the deep power-down mode when a standard command is inputted to the standard command I/F circuit and recovers the internal circuit from the DPD mode in the case where the deep power-down mode is detected. The standard command is executed after the internal circuit is recovered.

Abstract: A semiconductor device capable of automatically transitioning from a standby mode to a deep power down (DPD) mode is provided. The semiconductor device includes: internal circuits capable of operating in response to an input signal from an input/output circuit; and a controller capable of controlling operations of the internal circuits. The internal circuit supporting the DPD mode includes: a measurement part, measuring a time since a time point of the semiconductor device entering the standby mode; a transition time detection part, detecting a case where a measurement time of the measurement part has reached a certain time; and a DPD signal generation part, generating a power down enable signal for further reducing power consumption in the standby mode when a transition time is detected.

Abstract: A semiconductor device that can automatically transition from a standby mode to a deep power down (DPD) mode is provided. The semiconductor device includes a DPD controller supporting the DPD mode and multiple internal circuits. The DPD controller measures a time since a time point of entering the standby mode and generates multiple power down enable signals for further reducing power consumption in the standby mode in response to elapse of a measurement time, so that operations of the multiple internal circuits are stopped in stages.

Abstract: A semiconductor device 50 of the invention includes a supply voltage VCC, a plurality of registers 14, a PMOS transistor P, an AND gate 12, and a determination circuit 16. The registers 14 include a first register and a second register. The first register can keep data, and the second register can keep a check bit. The PMOS transistor P and the AND gate 12 are both connected between the supply voltage VCC and the registers 14, and both control the supply from the supply voltage VCC to the registers 14. The determination circuit 16 determines whether the check bit kept in the second register is correct or not in a DPD (deep-power-down) mode. An operating margin of the second register is worse than that of the first register. While the determination circuit 16 determines that the check bit kept in the second register is incorrect, the PMOS transistor P provides the supply voltage VCC to the registers 14.

Abstract: A semiconductor memory device that can reduce power consumption and precisely perform a power-down operation while a testing operation is underway is provided. A flash memory of the invention has a low-power voltage-detection circuit, a high-precision voltage-detection circuit, and a controller. The low-power voltage-detection circuit detects the supply voltage falling to a constant voltage. The high-precision voltage-detection circuit detects the supply voltage falling to the constant voltage. The controller selects the high-precision voltage-detection circuit when the internal circuit is being tested, and it selects the low-power voltage-detection circuit when the internal circuit is not undergoing a test. The controller responds to the detection result from the low-power voltage-detection circuit or the high-precision voltage-detection circuit by performing a power-down operation.

Abstract: A semiconductor memory device, which can reduce consuming power and perform a power-off operation correctly, is provided. A flash memory of the invention includes: a low-power-voltage detection circuit detecting that a supply voltage drops to a given voltage; a high-accuracy voltage detection circuit detecting that the supply voltage drops to the given voltage; and a controller selecting the high-accuracy voltage detection circuit when an internal circuit is in an operation state, selecting the low-power-voltage detection circuit when the internal circuit is in a standby state, and performing a power-off operation in response to a detection result of the low-power-voltage detection circuit or the high-accuracy voltage detection circuit.

Abstract: The present invention provides a semiconductor memory device capable of performing rapid erasing while reducing power consumption. In the flash memory of the present invention, the voltage of the P well is detected by the voltage detecting unit 200 during the erasing operation. When the voltage is lower than the threshold value, it is determined that the off leakage current of the selection transistor of the non-selection block is large, and the voltage of the global word line at the time of applying the next erase pulse is increased. When the voltage is above the threshold value, it is determined that the off leakage current is small, and the voltage of the global word line at the time of applying the next erase pulse is maintained.

Abstract: A semiconductor storage apparatus capable of realizing continuous read with high speed is provided. A continuous read method of a NAND flash memory includes: a step for holding setting information related to a read time of a memory cell array in continuous read in a register; a step for reading data from the memory cell array in the read time based on the setting information; a step for holding the read data in a latch (L1) and a latch (L2); and a step for outputting the data held synchronously with an external clock signal corresponding to the setting information.