Patents by Inventor Naoaki Sugimura

Naoaki Sugimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240361399
    Abstract: A battery monitoring system includes at least one group of a plurality of battery cells connected in series and including a first battery cell at a highest potential and a second battery cell at a lowest potential; and a first semiconductor device capable of measuring a voltage of the at least one group of the battery cells. The first semiconductor device includes: a first terminal connected to a high potential side of the first battery cell through a first filter, the first filter being connected to a low potential side of the second battery cell; a second terminal connected to the high potential side of the first battery cell through a second filter, the second filter being connected to the low potential side of the second battery cell; a first discharge circuit connected to the first terminal; and a first circuit connected to the second terminal.
    Type: Application
    Filed: July 6, 2024
    Publication date: October 31, 2024
    Inventor: Naoaki SUGIMURA
  • Patent number: 12055598
    Abstract: A battery monitoring system includes a first group of a plurality of battery cells connected in series and including a first battery cell at a highest potential and a second battery cell at a lowest potential; a second group of a plurality of battery cells connected in series and including a third battery cell at a highest potential and a fourth battery cell at a lowest potential, the second group of the battery cells being connected to the first group of the battery cells in series; and first and second semiconductor devices capable of measuring a voltage of the first group of the battery cells and a voltage of the second group of the battery cells, respectively.
    Type: Grant
    Filed: June 20, 2023
    Date of Patent: August 6, 2024
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventor: Naoaki Sugimura
  • Publication number: 20230366950
    Abstract: A battery monitoring system includes a first group of a plurality of battery cells connected in series and including a first battery cell at a highest potential and a second battery cell at a lowest potential; a second group of a plurality of battery cells connected in series and including a third battery cell at a highest potential and a fourth battery cell at a lowest potential, the second group of the battery cells being connected to the first group of the battery cells in series; and first and second semiconductor devices capable of measuring a voltage of the first group of the battery cells and a voltage of the second group of the battery cells, respectively.
    Type: Application
    Filed: June 20, 2023
    Publication date: November 16, 2023
    Inventor: Naoaki SUGIMURA
  • Patent number: 11719756
    Abstract: A battery monitoring system includes a plurality of battery cells connected in series; a cell voltage measurement circuit for measuring a voltage of the battery cells; a first terminal connected to the cell voltage measurement circuit; a second terminal isolated from the cell voltage measurement circuit; a plurality of protection elements each corresponding to each of the battery cells; and a protection circuit connected to the second terminal for discharging an electric current from the protection elements through the second terminal.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: August 8, 2023
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Naoaki Sugimura
  • Publication number: 20210318389
    Abstract: A battery monitoring system includes a plurality of battery cells connected in series; a cell voltage measurement circuit for measuring a voltage of the battery cells; a first terminal connected to the cell voltage measurement circuit; a second terminal isolated from the cell voltage measurement circuit; a plurality of protection elements each corresponding to each of the battery cells; and a protection circuit connected to the second terminal for discharging an electric current from the protection elements through the second terminal.
    Type: Application
    Filed: June 23, 2021
    Publication date: October 14, 2021
    Inventor: Naoaki SUGIMURA
  • Patent number: 11073569
    Abstract: A battery monitoring system includes a plurality of battery cells connected in series; a cell voltage measurement circuit for measuring a voltage of the battery cells; a first terminal connected to the cell voltage measurement circuit; a second terminal isolated from the cell voltage measurement circuit; a plurality of protection elements each corresponding to each of the battery cells; and a protection circuit connected to the second terminal for discharging an electric current from the protection elements through the second terminal.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: July 27, 2021
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventor: Naoaki Sugimura
  • Patent number: 10930981
    Abstract: A semiconductor device includes: a boosting section configured to output a second voltage boosted from a first voltage; a voltage lowering section configured to output a lowered voltage that has been lowered from the second voltage by a predetermined voltage; a first buffer amp including a non-inverting input terminal connected to an output of the voltage lowering section; a second buffer amp including a non-inverting input terminal that is input with the first voltage; and a difference output section configured to output a voltage corresponding to a difference between output of the first buffer amp and output of the second buffer amp.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: February 23, 2021
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Naoaki Sugimura
  • Publication number: 20200295409
    Abstract: A semiconductor device includes: a boosting section configured to output a second voltage boosted from a first voltage; a voltage lowering section configured to output a lowered voltage that has been lowered from the second voltage by a predetermined voltage; a first buffer amp including a non-inverting input terminal connected to an output of the voltage lowering section; a second buffer amp including a non-inverting input terminal that is input with the first voltage; and a difference output section configured to output a voltage corresponding to a difference between output of the first buffer amp and output of the second buffer amp.
    Type: Application
    Filed: June 2, 2020
    Publication date: September 17, 2020
    Inventor: NAOAKI SUGIMURA
  • Patent number: 10705148
    Abstract: A semiconductor device includes: a boosting section configured to output a second voltage boosted from a first voltage; a voltage lowering section configured to output a lowered voltage that has been lowered from the second voltage by a predetermined voltage; a first buffer amp including a non-inverting input terminal connected to an output of the voltage lowering section; a second buffer amp including a non-inverting input terminal that is input with the first voltage; and a difference output section configured to output a voltage corresponding to a difference between output of the first buffer amp and output of the second buffer amp.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: July 7, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Naoaki Sugimura
  • Patent number: 10693301
    Abstract: A semiconductor device including a first buffer amplifier into which a voltage of a high potential side of one battery cell selected from plural battery cells that are connected in series is input; a second buffer amplifier into which a voltage of a low potential side of the one battery cell other than a lowermost stage battery cell is input; an analog level shifter into which a voltage output from the first buffer amplifier and a voltage output from the buffer amplifier are input; a first switch that switches a voltage input to the analog level shifter from the voltage output from the second buffer amplifier to a reference voltage; and a second switch that switches a voltage input to the first buffer amplifier from the voltage of the high potential side of the one battery cell to the reference voltage.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: June 23, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Naoaki Sugimura
  • Publication number: 20200081071
    Abstract: A battery monitoring system includes a plurality of battery cells connected in series; a cell voltage measurement circuit for measuring a voltage of the battery cells; a first terminal connected to the cell voltage measurement circuit; a second terminal isolated from the cell voltage measurement circuit; a plurality of protection elements each corresponding to each of the battery cells; and a protection circuit connected to the second terminal for discharging an electric current from the protection elements through the second terminal.
    Type: Application
    Filed: November 15, 2019
    Publication date: March 12, 2020
    Inventor: Naoaki SUGIMURA
  • Patent number: 10502795
    Abstract: A battery monitoring system includes a plurality of battery cells connected in series; a cell voltage measurement circuit for measuring a voltage of the battery cells; a first terminal connected to the cell voltage measurement circuit; a second terminal having a potential higher than that of the first terminal; and a protection circuit connected to the second terminal for discharging an electric current to the second terminal so that the cell voltage measurement circuit is protected.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: December 10, 2019
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventor: Naoaki Sugimura
  • Patent number: 10401434
    Abstract: A semiconductor device including plural first switches, each provided so as to correspond to one of plural battery cells connected in series, each first switch including one end connected to a corresponding battery cell and another end connected to one electrode of a corresponding charge storage section of plural charge storage sections, each of the charge storage sections being provided so as to correspond to one of the plural battery cells, and another electrode of each charge storage section being connected to a fixed potential; plural second switches, each provided so as to correspond to one of the plural first switches, each second switch including one end connected to the other end of the corresponding first switch; and processing section connected to each other end of the plural second switches, that processes voltages supplied via the second switches.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: September 3, 2019
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Hisao Ohtake, Naoaki Sugimura
  • Patent number: 10330736
    Abstract: A semiconductor device for measuring a voltage of a battery cell, including first and second nodes, and first and second battery voltage measurement units. The first node is configured to receive a first voltage, the first voltage being a voltage of a capacitor that accumulates an electric charge based on the voltage of the battery cell. The first battery voltage measurement unit measures the first voltage through a first path. The second node is configured to receive a second voltage based on the voltage of the battery cell, the second node being different from the first node. The second battery voltage measurement unit measures the second voltage through a second path that is different from the first path.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: June 25, 2019
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventors: Masaru Sekiguchi, Hidekazu Kikuchi, Naoaki Sugimura
  • Patent number: 10247785
    Abstract: An assembled-battery system, a semiconductor circuit, and a diagnostic method enables appropriate self-diagnosis of a measuring unit. An output value (A-B) output from an analog-to-digital converter through power-supply lines, a cell-selection switch, and a level shifter is summed with an output value (B-VSS) obtained by a directly input reference voltage B being output from the analog-to-digital converter. When the summed value is considered equal the reference voltage A—the voltage VSS, it is diagnosed that an abnormality such as a breakdown has not occurred.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: April 2, 2019
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Naoaki Sugimura, Takaaki Izawa
  • Publication number: 20190004116
    Abstract: A semiconductor device includes: a boosting section configured to output a second voltage boosted from a first voltage; a voltage lowering section configured to output a lowered voltage that has been lowered from the second voltage by a predetermined voltage; a first buffer amp including a non-inverting input terminal connected to an output of the voltage lowering section; a second buffer amp including a non-inverting input terminal that is input with the first voltage; and a difference output section configured to output a voltage corresponding to a difference between output of the first buffer amp and output of the second buffer amp.
    Type: Application
    Filed: June 26, 2018
    Publication date: January 3, 2019
    Inventor: NAOAKI SUGIMURA
  • Publication number: 20180241226
    Abstract: A semiconductor device including a first buffer amplifier into which a voltage of a high potential side of one battery cell selected from plural battery cells that are connected in series is input; a second buffer amplifier into which a voltage of a low potential side of the one battery cell other than a lowermost stage battery cell is input; an analog level shifter into which a voltage output from the first buffer amplifier and a voltage output from the buffer amplifier are input; a first switch that switches a voltage input to the analog level shifter from the voltage output from the second buffer amplifier to a reference voltage; and a second switch that switches a voltage input to the first buffer amplifier from the voltage of the high potential side of the one battery cell to the reference voltage.
    Type: Application
    Filed: April 24, 2018
    Publication date: August 23, 2018
    Inventor: Naoaki SUGIMURA
  • Patent number: 9966768
    Abstract: The present disclosure provides a semiconductor device including: a first buffer amplifier into which a voltage of a high potential side of one battery cell selected from plural battery cells that are connected in series is input; a second buffer amplifier into which a voltage of a low potential side of the one battery cell other than a lowermost stage battery cell is input; an analog level shifter into which a voltage output from the first buffer amplifier and a voltage output from, the buffer amplifier are input; a first switch that switches a voltage input to the analog level shifter from the voltage output from the second buffer amplifier to a reference voltage; and a second switch that switches a voltage input to the first buffer amplifier from the voltage of the high potential side of the one battery cell to the reference voltage.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: May 8, 2018
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Naoaki Sugimura
  • Patent number: 9857432
    Abstract: The present invention appropriately detects line-breakages in a signal line related to a battery connected to a discharge circuit for discharging. Namely, an initialization operation produces a state in which a capacitor (C1) is charged with the difference between the voltage of a signal line (Vn) and a self-threshold voltage (Vx), and a capacitor (C2) is charged with the difference between the voltage of a signal line (Vn?1) and a self-threshold voltage (Vx), in a comparison circuit (26). In a comparison operation, a voltage adjusting section (ILn+1) produces a state in which line-breakage detection current is drawn out from a signal line (Ln), a signal line (Lc) is connected to the capacitors (C1, C2) and a voltage (DVn) is input to the capacitors (C1, C2). When an output OUT=L level, it is detected that there is no line-breakage, and when the output OUT=H level, it is detected that there is a line-breakage.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: January 2, 2018
    Assignees: LAPIS SEMICONDUCTOR CO., LTD., YAZAKI CORPORATION
    Inventors: Naoaki Sugimura, Takaaki Izawa
  • Publication number: 20170184678
    Abstract: A semiconductor device for measuring a voltage of a battery cell, including first and second nodes, and first and second battery voltage measurement units. The first node is configured to receive a first voltage, the first voltage being a voltage of a capacitor that accumulates an electric charge based on the voltage of the battery cell. The first battery voltage measurement unit measures the first voltage through a first path. The second node is configured to receive a second voltage based on the voltage of the battery cell, the second node being different from the first node. The second battery voltage measurement unit measures the second voltage through a second path that is different from the first path.
    Type: Application
    Filed: December 20, 2016
    Publication date: June 29, 2017
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Masaru SEKIGUCHI, Hidekazu KIKUCHI, Naoaki SUGIMURA