Patents by Inventor Naoaki Yamanaka

Naoaki Yamanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120300923
    Abstract: Technologies are generally described for providing an encryption method using real-world objects. In some examples, a method may include capturing, by a first electronic device, an external object, generating an object signal associated with the external object, generating an encryption key based on the object signal, and transmitting data encrypted by the encryption key to a second electronic device.
    Type: Application
    Filed: May 24, 2011
    Publication date: November 29, 2012
    Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventors: Yutaka Arakawa, Naoaki Yamanaka, Eiji Oki
  • Publication number: 20120154269
    Abstract: An object can be displayed on a screen of a two-dimensional coordinate system based on xyz-coordinate values of the object in a three-dimensional coordinate system, operation information of a two-dimensional coordinate system with respect to the object can be received from an input device, and whether the operation information is in accordance with a predetermined rule or not is determined. If the operation information is not in accordance with the predetermined rule, xy-coordinate values of the object can be updated in accordance with the operation information. If the operation information is in accordance with the predetermined rule, a z-coordinate value of the object can be updated in accordance with the operation information.
    Type: Application
    Filed: April 26, 2011
    Publication date: June 21, 2012
    Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventors: Eiji Oki, Naoaki Yamanaka, Yutaka Arakawa
  • Patent number: 7978713
    Abstract: A network is realized having GMPLS and IP/MPLS mixed, in which an IP/MPLS node can be operated as is without replacing the IP/MPLS node with a node having a GMPLS function, even if the GMPLS and IP/MPLS are mixed. To match with the protocol of the IP/MPLS node outside of a GMPLS cloud, the GMPLS+IP/MPLS node (edge) establishes a PSC-LSP between GMPLS+IP/MPLS nodes (edge), uses the PSC-LSP as an IP/MPLS link from the viewpoint of the IP/MPLS node, and operates signaling of an MPLS-LSP establishment requested from the IP/MPLS.
    Type: Grant
    Filed: March 24, 2004
    Date of Patent: July 12, 2011
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Eiji Oki, Daisaku Shimazaki, Kohei Shiomoto, Naoaki Yamanaka
  • Publication number: 20110123193
    Abstract: In an access network using optical switches, communications between an OLT and ONUs are established without a photoelectric conversion performed at an optical switching unit. The OLT controls the downlink optical switch SW(DOWN) to sequentially select each ONU in slots arranged in a discrete manner, and transmits a Discovery Gate message. Upon receipt of the Discovery Gate message, each ONU consecutively transmits Register Request messages. The uplink optical switch SW(UP) sequentially switch signals from ONU#1 through ONU#128 in the slots arranged in a discrete manner, and outputs the signals to the OLT, Some of the Register Requests transmitted from the respective ONUs pass through the SW(UP), and reach the OLT. Based on the received Register Requests, the OLT determines the timing of transmission for the ONUS, and notifies the ONUS of the timing of transmission through a Gate message.
    Type: Application
    Filed: July 3, 2009
    Publication date: May 26, 2011
    Applicant: KEIO UNIVERSITY
    Inventors: Naoaki Yamanaka, Yutaka Arakawa, Kazumasa Tokuhashi
  • Patent number: 7894368
    Abstract: An OVPN user register an L1 signal type information which is used in the user's device in an OVPN terminating device in advance together with an IP address and a VPNID which are allocated to the user's device. Registered contents are notified to other OVPN terminating devices which control the same VPNID as that of the user's device. Otherwise, when a calling connection request arrives from the user's device, the registered contents are notified other OVPN terminating devices which control the devices which receive the notification. By doing this, it is possible to handle a request by the user for changing the setting for the signal format which is employed in the user's device quickly. Also, it is possible to realize an OVPN which can perform a process for a calling connection request from the user efficiently and improve an operability for the user.
    Type: Grant
    Filed: December 3, 2003
    Date of Patent: February 22, 2011
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Akira Misawa, Satoru Okamoto, Masaru Katayama, Naoaki Yamanaka
  • Patent number: 7545829
    Abstract: A layered network node of which a network it belongs is divided up into cells which are constituted by a plurality of nodes; the cells are defined as virtual nodes; if links exist which connect the interiors of the virtual nodes and the exterior, contact points between them are defined as interfaces of the virtual nodes; the virtual network constituted by the virtual nodes is further divided up into cells and making them into virtual nodes; said virtual network is defined as a network of a higher level with respect to the initial virtual network; by performing said operation of division into cells and making into virtual nodes once or a plurality of times, the layered network is constituted; path computation is performed from the source node to a destination node in a stepwise manner by dispersing it over the various layers.
    Type: Grant
    Filed: October 3, 2003
    Date of Patent: June 9, 2009
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Daisaku Shimazaki, Eiji Oki, Naoaki Yamanaka
  • Patent number: 7474664
    Abstract: An ATM switch includes a first stage, a second stage and a third stage each of which stages includes at least one basic switch, wherein the first stage, the second stage and the third stage are connected. The basic switch includes a part which refers to time information written in a header of an input cell and switches cells to an output port in an ascending order of the time information. In addition, the ATM switch includes a cell distribution part in the basic switch of the first stage. The cell distribution part determines a routes of a cell to be transferred such that loads of routes within the ATM switch are balanced. The ATM switch further includes an adding part which adds arriving time information to an arriving cell as the time information.
    Type: Grant
    Filed: October 22, 2004
    Date of Patent: January 6, 2009
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Seisho Yasukawa, Naoki Takaya, Masayoshi Nabeshima, Eiji Oki, Naoaki Yamanaka
  • Patent number: 7457240
    Abstract: The present invention relates to a node, a packet communication network, and a packet communication method and program. The node of the present invention is one which includes a section which advertises to other nodes link state information which indicates the state of links which are connected to this node, a section which establishes a packet forwarding path according to the link state information which is included in the advertisement by the advertisement section, and a traffic observation section which observes the traffic and outputs its observations as traffic observation results.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: November 25, 2008
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Eiji Oki, Daisaku Shimazaki, Naoaki Yamanaka
  • Patent number: 7339935
    Abstract: An ATM switch includes a first stage, a second stage and a third stage each of which stages includes at least one basic switch, wherein the first stage, the second stage and the third stage are connected. The basic switch includes a part which refers to time information written in a header of an input cell and switches cells to an output port in an ascending order of the time information. In addition, the ATM switch includes a cell distribution part in the basic switch of the first stage. The cell distribution part determines a routes of a cell to be transferred such that loads of routes within the ATM switch are balanced. The ATM switch further includes an adding part which adds arriving time information to an arriving cell as the time information.
    Type: Grant
    Filed: October 22, 2004
    Date of Patent: March 4, 2008
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Seisho Yasukawa, Naoki Takaya, Masayoshi Nabeshima, Eiji Oki, Naoaki Yamanaka
  • Patent number: 7333424
    Abstract: An upper layer node is used in a multi-layer network which includes an upper layer network which performs switching and transfer in units of packets, and a lower layer network which includes optical transmission lines and optical switches and accommodate the upper layer network; this upper layer node being connected to the lower layer network which includes lower layer nodes including obstruction restoration sections, and transmission lines, and including: a section which detects the occurrence of an obstruction upon a transmission line which it accommodates; a section which advertises the detection result as obstruction information; a section which retains the topology information for the network; a section which updates the retained topology information according to advertised obstruction information, or obstruction information which it has detected; and an advertisement transfer section which advertises to other upper layer nodes the advertised obstruction information.
    Type: Grant
    Filed: March 5, 2003
    Date of Patent: February 19, 2008
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Naoaki Yamanaka, Eiji Oki, Kohei Shiomoto, Satoru Okamoto, Wataru Imajuku
  • Patent number: 7313328
    Abstract: A multi-layer photonic network and nodes used therein are provided. The multi-layer photonic network comprises a packet network which performs switching and transfer in packet units, and a photonic network comprising optical transmission lines and photonic switches, and which accommodates the packet network. The multi-layer photonic network also has a two layer structure of optical wavelength links (O-LSPs) and packet links (E-LSPs). The O-LSPs are constituted by the optical transmission lines and comprise optical wavelength switching capability (LSC) which is capable of switching in optical wavelength units and packet switching capability (PSC) which is capable of switching in packet units at both their ends. The E-LSPs include the O-LSPs and PSCs at both their ends. Each node includes a section for automatically establishing an O-LSP according to an establishment request for an E-LSP while taking account of path information including path cost, resource consumption, and traffic quantity.
    Type: Grant
    Filed: February 25, 2003
    Date of Patent: December 25, 2007
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Eiji Oki, Wataru Imajuku, Kohei Shiomoto, Naoaki Yamanaka, Daisaku Shimazaki, Naohide Nagatsu, Yoshihiro Takikawa
  • Publication number: 20070263544
    Abstract: There is provided a system that uses a network matrix to carry out a search for shortest paths from a starting node included in a network having a plurality of nodes to other nodes. The network matrix includes link costs of links and each link has a root end that is a node included in the network and a tail end that is another node connected to the root end.
    Type: Application
    Filed: November 21, 2006
    Publication date: November 15, 2007
    Applicants: IPFLEX INC., KEIO UNIVERSITY
    Inventors: Naoaki Yamanaka, Hiroyuki Ishikawa, Yutaka Arakawa, Sho Shimizu, Kosuke Shiba
  • Patent number: 7292576
    Abstract: An ATM switch includes a first stage, a second stage and a third stage each of which stages includes at least one basic switch, wherein the first stage, the second stage and the third stage are connected. The basic switch includes a part which refers to time information written in a header of an input cell and switches cells to an output port in an ascending order of the time information. In addition, the ATM switch includes a cell distribution part in the basic switch of the first stage. The cell distribution part determines a routes of a cell to be transferred such that loads of routes within the ATM switch are balanced. The ATM switch further includes an adding part which adds arriving time information to an arriving cell as the time information.
    Type: Grant
    Filed: October 22, 2004
    Date of Patent: November 6, 2007
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Seisho Yasukawa, Naoki Takaya, Masayoshi Nabeshima, Eiji Oki, Naoaki Yamanaka
  • Patent number: 7289730
    Abstract: A source node, along with transmitting an optical path setup request, notifies towards a destination node available resource information related to itself, pre-assigns the available resources which its own node has notified. Each of transit nodes, along with relaying towards the destination node the optical path setup request which has been received from a previous hop node, notifies towards the destination node available resource information related to itself, and pre-assigns the available resources which each of their own nodes has notified. The destination node, along with reserving a resource which is to be used for setting up an optical path based upon an optical path setup request which has been received, transmits a resource reservation request towards the source node. The transit nodes and the source node actually reserve an available resource which has been pre-assigned, based upon a resource reservation request from a next hop node.
    Type: Grant
    Filed: April 16, 2003
    Date of Patent: October 30, 2007
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Nobuaki Matsuura, Naoaki Yamanaka, Wataru Imajuku, Eiji Oki
  • Patent number: 7263289
    Abstract: The present invention relates to a node used in an optical communication network, and comprises functions for transferring and receiving data, and a unit for establishing and releasing a cut through path to a node of the next stage, the establishing and releasing unit having a detecting unit which detects the arrival of a request packet for establishing a cut through path to the node stage.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: August 28, 2007
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Kohei Shiomoto, Naoaki Yamanaka, Eiji Oki
  • Patent number: 7200330
    Abstract: The present invention relates to a node which is used in the structure of an optical communication network. This node has a signal transmission function for performing data transfer and a signal receiving function for performing data signal reception, and includes a unit for establishing and releasing a cut through path to a next stage node. Moreover, it includes a unit for detecting the arrival of a leading packet of burst data, and the unit for establishing and releasing the cut through path includes a unit for establishing a cut through path to the next stage node, when the arrival of a leading packet of burst data is detected by the leading packet arrival detection unit.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: April 3, 2007
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Kohei Shiomoto, Naoaki Yamanaka, Eiji Oki
  • Patent number: 7136391
    Abstract: An ATM switch includes a first stage, a second stage and a third stage each of which stages includes at least one basic switch, wherein the first stage, the second stage and the third stage are connected. The basic switch includes a part which refers to time information written in a header of an input cell and switches cells to an output port in an ascending order of the time information. In addition, the ATM switch includes a cell distribution part in the basic switch of the first stage. The cell distribution part determines a routes of a cell to be transferred such that loads of routes within the ATM switch are balanced. The ATM switch further includes an adding part which adds arriving time information to an arriving cell as the time information.
    Type: Grant
    Filed: August 18, 1999
    Date of Patent: November 14, 2006
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Seisho Yasukawa, Naoki Takaya, Masayoshi Nabeshima, Eiji Oki, Naoaki Yamanaka
  • Publication number: 20060018313
    Abstract: A network is realized having GMPLS and IP/MPLS mixed, in which an IP/MPLS node can be operated as is without replacing the IP/MPLS node with a node having a GMPLS function, even if the GMPLS and IP/MPLS are mixed. To match with the protocol of the IP/MPLS node outside of a GMPLS cloud, the GMPLS+IP/MPLS node (edge) establishes a PSC-LSP between GMPLS+IP/MPLS nodes (edge), uses the PSC-LSP as an IP/MPLS link from the viewpoint of the IP/MPLS node, and operates signaling of an MPLS-LSP establishment requested from the IP/MPLS.
    Type: Application
    Filed: March 24, 2004
    Publication date: January 26, 2006
    Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Eiji Oki, Daisaku Shimazaki, Kohei Shiomoto, Naoaki Yamanaka
  • Publication number: 20050083939
    Abstract: An ATM switch includes a first stage, a second stage and a third stage each of which stages includes at least one basic switch, wherein the first stage, the second stage and the third stage are connected. The basic switch includes a part which refers to time information written in a header of an input cell and switches cells to an output port in an ascending order of the time information. In addition, the ATM switch includes a cell distribution part in the basic switch of the first stage. The cell distribution part determines a routes of a cell to be transferred such that loads of routes within the ATM switch are balanced. The ATM switch further includes an adding part which adds arriving time information to an arriving cell as the time information.
    Type: Application
    Filed: October 22, 2004
    Publication date: April 21, 2005
    Inventors: Seisho Yasukawa, Naoki Takaya, Masayoshi Nebeshima, Eiji Oki, Naoaki Yamanaka
  • Publication number: 20050053096
    Abstract: An ATM switch includes a first stage, a second stage and a third stage each of which stages includes at least one basic switch, wherein the first stage, the second stage and the third stage are connected. The basic switch includes a part which refers to time information written in a header of an input cell and switches cells to an output port in an ascending order of the time information. In addition, the ATM switch includes a cell distribution part in the basic switch of the first stage. The cell distribution part determines a routes of a cell to be transferred such that loads of routes within the ATM switch are balanced. The ATM switch further includes an adding part which adds arriving time information to an arriving cell as the time information.
    Type: Application
    Filed: October 22, 2004
    Publication date: March 10, 2005
    Inventors: Seisho Yasukawa, Naoki Takaya, Masayoshi Nabeshima, Eiji Oki, Naoaki Yamanaka