Patents by Inventor Naobumi Tsuzuki

Naobumi Tsuzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4172261
    Abstract: A semiconductor device is provided with a metal header of a size sufficiently small such that only a semiconductor element holding plate which requires heat dissipation can be mounted thereon. The metal header supports at its upper fringe portion an apertured member having a penetrating opening sealed along the opening. An insulative outer frame having a thermal expansion coefficient of the same order as that of the apertured member is supported on the peripheral portion of the apertured member. A lid member for hermetic sealing is bonded onto the outer frame.
    Type: Grant
    Filed: January 10, 1978
    Date of Patent: October 23, 1979
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Naobumi Tsuzuki, Shinzo Anazawa
  • Patent number: 4092445
    Abstract: A process is disclosed for forming a porous region in a semiconductor device. In the process, a region of a relatively high impurity concentration is formed at a desired region of a semiconductor body of a lower impurity concentration. The semiconductor body is dipped into an electrolyte along with an electrode. The electrode is connected to the semiconductor body, whereby the high impurity concentration region is converted into a porous region.
    Type: Grant
    Filed: November 4, 1976
    Date of Patent: May 30, 1978
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Naobumi Tsuzuki, Tetsu Koji, Kazuo Noguchi
  • Patent number: 4067040
    Abstract: A semiconductor device, which provides efficient heat dissipation, includes a semiconductor support member formed of an insulating, thermally conductive material having a projecting portion on the top surface and a first conducting layer extending along the surfaces of the support members from the bottom to the projecting portion. An insulating wall member for installing terminals is disposed on the top surface of the semiconductor support member in areas around the projecting portion. A second conducting layer is formed on the top end face of the wall member, and a hollow portion is provided in the wall member below the second conducting layer.
    Type: Grant
    Filed: December 9, 1976
    Date of Patent: January 3, 1978
    Assignee: Nippon Electric Company, Ltd.
    Inventors: Naobumi Tsuzuki, Shinzo Anazawa, Shozo Noguchi