Patents by Inventor Naofumi Abiko
Naofumi Abiko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11901020Abstract: [Problem] To provide a semiconductor storage device capable of reducing the load on a controller. [Solution] According to one embodiment, a semiconductor storage device 2 includes a memory cell array 110 including a plurality of memory cell transistors MT, a plurality of word lines WL connected to gates of the respective memory cell arrays 110, a voltage generation circuit 43 generating a voltage applied to each of the word lines WL, and a sequencer 41 controlling an operation of the memory cell array 110. The sequencer 41 repeats a loop including a program operation and a verify operation multiple times in a write operation. The sequencer 41 controls an operation of the voltage generation circuit 43 so that a rate increase in a voltage applied to a non-selected word line in the verify operation of a last loop is smaller than the rate increase in the voltage applied to the non-selected word line in the verify operation of a first loop.Type: GrantFiled: August 27, 2021Date of Patent: February 13, 2024Assignee: Kioxia CorporationInventors: Emiri Takada, Naofumi Abiko
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Publication number: 20240046974Abstract: A semiconductor memory device includes a memory cell, a word line connected to the memory cell, a source line connected to the memory cell, a bit line connected to the memory cell, and a control circuit configured to perform a read operation on the memory cell. During the read operation, the control circuit applies to the word line a first voltage, a second voltage greater than the first voltage after applying the first voltage, and a third voltage greater than the first voltage and smaller than the second voltage after applying the second voltage, and applies to the source line a fourth voltage according to a timing at which the second voltage is applied to the word line, a fifth voltage smaller than the fourth voltage after applying the fourth voltage, and a sixth voltage greater than the fifth voltage after applying the fifth voltage.Type: ApplicationFiled: October 19, 2023Publication date: February 8, 2024Inventors: Toshifumi WATANABE, Naofumi ABIKO
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Publication number: 20240029805Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells, a first word line, first and second sense amplifiers, first and second bit lines, a controller. The first and second sense amplifiers each include first and second transistors. The first bit line is connected between the first memory cell and the first transistor. The second bit line is connected between the second memory cell and the second transistor. In the read operation, the controller is configured to apply a kick voltage to the first word line before applying the read voltage to the first word line, and to apply a first voltage to a gate of the first transistor and a second voltage to a gate of the second transistor while applying the kick voltage to the first word line.Type: ApplicationFiled: October 6, 2023Publication date: January 25, 2024Applicant: KIOXIA CORPORATIONInventors: Yoshihiko KAMATA, Naofumi ABIKO
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Publication number: 20230420054Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.Type: ApplicationFiled: September 7, 2023Publication date: December 28, 2023Applicant: Kioxia CorporationInventors: Akio SUGAHARA, Akihiro IMAMOTO, Toshifumi WATANABE, Mami KAKOI, Kohei MASUDA, Masahiro YOSHIHARA, Naofumi ABIKO
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Patent number: 11842759Abstract: A semiconductor memory device includes a memory cell, a word line connected to the memory cell, a source line connected to the memory cell, a bit line connected to the memory cell, and a control circuit configured to perform a read operation on the memory cell. During the read operation, the control circuit applies to the word line a first voltage, a second voltage greater than the first voltage after applying the first voltage, and a third voltage greater than the first voltage and smaller than the second voltage after applying the second voltage, and applies to the source line a fourth voltage according to a timing at which the second voltage is applied to the word line, a fifth voltage smaller than the fourth voltage after applying the fourth voltage, and a sixth voltage greater than the fifth voltage after applying the fifth voltage.Type: GrantFiled: July 26, 2022Date of Patent: December 12, 2023Assignee: Kioxia CorporationInventors: Toshifumi Watanabe, Naofumi Abiko
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Patent number: 11837295Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells, a first word line, first and second sense amplifiers, first and second bit lines, a controller. The first and second sense amplifiers each include first and second transistors. The first bit line is connected between the first memory cell and the first transistor. The second bit line is connected between the second memory cell and the second transistor. In the read operation, the controller is configured to apply a kick voltage to the first word line before applying the read voltage to the first word line, and to apply a first voltage to a gate of the first transistor and a second voltage to a gate of the second transistor while applying the kick voltage to the first word line.Type: GrantFiled: June 15, 2022Date of Patent: December 5, 2023Assignee: KIOXIA CORPORATIONInventors: Yoshihiko Kamata, Naofumi Abiko
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Patent number: 11783899Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.Type: GrantFiled: October 26, 2022Date of Patent: October 10, 2023Assignee: Kioxia CorporationInventors: Akio Sugahara, Akihiro Imamoto, Toshifumi Watanabe, Mami Kakoi, Kohei Masuda, Masahiro Yoshihara, Naofumi Abiko
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Publication number: 20230186984Abstract: A semiconductor memory device includes memory cell transistors and a control circuit. In a write operation, the control circuit executes multiple loops each including a program operation, a verify operation, and a bit scan operation. In the bit scan operation, the control circuit performs, a first process of generating verify result data in parallel for a group of memory cell transistors having different target threshold voltage states, the verify result data for each memory cell transistor in the group indicating whether the memory cell transistor has reached its target threshold voltage state, and a second process of calculating for each of the target threshold voltage states, the number of memory cell transistors that have not reached their target threshold voltage states.Type: ApplicationFiled: August 26, 2022Publication date: June 15, 2023Inventor: Naofumi ABIKO
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Publication number: 20230052383Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.Type: ApplicationFiled: October 26, 2022Publication date: February 16, 2023Applicant: Kioxia CorporationInventors: Akio SUGAHARA, Akihiro IMAMOTO, Toshifumi WATANABE, Mami KAKOI, Kohei MASUDA, Masahiro YOSHIHARA, Naofumi ABIKO
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Patent number: 11532363Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation, and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.Type: GrantFiled: March 15, 2021Date of Patent: December 20, 2022Assignee: KIOXIA CORPORATIONInventors: Akio Sugahara, Akihiro Imamoto, Toshifumi Watanabe, Mami Kakoi, Kohei Masuda, Masahiro Yoshihara, Naofumi Abiko
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Publication number: 20220358991Abstract: A semiconductor memory device includes a memory cell, a word line connected to the memory cell, a source line connected to the memory cell, a bit line connected to the memory cell, and a control circuit configured to perform a read operation on the memory cell. During the read operation, the control circuit applies to the word line a first voltage, a second voltage greater than the first voltage after applying the first voltage, and a third voltage greater than the first voltage and smaller than the second voltage after applying the second voltage, and applies to the source line a fourth voltage according to a timing at which the second voltage is applied to the word line, a fifth voltage smaller than the fourth voltage after applying the fourth voltage, and a sixth voltage greater than the fifth voltage after applying the fifth voltage.Type: ApplicationFiled: July 26, 2022Publication date: November 10, 2022Inventors: Toshifumi WATANABE, Naofumi ABIKO
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Publication number: 20220310180Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells, a first word line, first and second sense amplifiers, first and second bit lines, a controller. The first and second sense amplifiers each include first and second transistors. The first bit line is connected between the first memory cell and the first transistor. The second bit line is connected between the second memory cell and the second transistor. In the read operation, the controller is configured to apply a kick voltage to the first word line before applying the read voltage to the first word line, and to apply a first voltage to a gate of the first transistor and a second voltage to a gate of the second transistor while applying the kick voltage to the first word line.Type: ApplicationFiled: June 15, 2022Publication date: September 29, 2022Applicant: KIOXIA CORPORATIONInventors: Yoshihiko KAMATA, Naofumi ABIKO
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Publication number: 20220284972Abstract: A semiconductor storage device includes a memory cell array includes a plurality of memory cell transistors, a plurality of word lines connected to gates of the memory cell transistors, a voltage generation circuit configured to generate a voltage applied to each of the word lines, and a control circuit configured to control an operation of the memory cell array. In a write operation for writing data to the memory cell array that includes multiple loops of a program operation and a verify operation, the control circuit controls an operation of the voltage generation circuit so that a rate of increase of a voltage applied to a non-selected word line at a beginning of the verify operation is different for at least two of the loops.Type: ApplicationFiled: August 27, 2021Publication date: September 8, 2022Inventors: Emiri TAKADA, Naofumi ABIKO
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Patent number: 11430502Abstract: A semiconductor memory device includes a memory cell, a word line connected to the memory cell, a source line connected to the memory cell, a bit line connected to the memory cell, and a control circuit configured to perform a read operation on the memory cell. During the read operation, the control circuit applies to the word line a first voltage, a second voltage greater than the first voltage after applying the first voltage, and a third voltage greater than the first voltage and smaller than the second voltage after applying the second voltage, and applies to the source line a fourth voltage according to a timing at which the second voltage is applied to the word line, a fifth voltage smaller than the fourth voltage after applying the fourth voltage, and a sixth voltage greater than the fifth voltage after applying the fifth voltage.Type: GrantFiled: April 5, 2021Date of Patent: August 30, 2022Assignee: KIOXIA CORPORATIONInventors: Toshifumi Watanabe, Naofumi Abiko
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Patent number: 11393545Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells, a first word line, first and second sense amplifiers, first and second bit lines, a controller. The first and second sense amplifiers each include first and second transistors. The first bit line is connected between the first memory cell and the first transistor. The second bit line is connected between the second memory cell and the second transistor. In the read operation, the controller is configured to apply a kick voltage to the first word line before applying the read voltage to the first word line, and to apply a first voltage to a gate of the first transistor and a second voltage to a gate of the second transistor while applying the kick voltage to the first word line.Type: GrantFiled: April 14, 2021Date of Patent: July 19, 2022Assignee: KIOXIA CORPORATIONInventors: Yoshihiko Kamata, Naofumi Abiko
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Patent number: 11328776Abstract: A semiconductor memory device includes first and second memory blocks arranged along a first direction, a first bit line extending in the first direction and including first and second portions respectively through which the first and second memory blocks are connected to the first bit line, a first sense amplifier connected to the first bit line, a first wiring which extends in a second direction intersecting the first direction, and overlaps the second portion of the first bit line when viewed in a third direction intersecting the first and second directions, and a controller which applies a first voltage to the first bit line, and a second voltage to the first wiring during a read operation. A first distance between the first sense amplifier and the first portion is shorter than a second distance between the first sense amplifier and the second portion.Type: GrantFiled: February 6, 2020Date of Patent: May 10, 2022Assignee: KIOXIA CORPORATIONInventor: Naofumi Abiko
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Patent number: 11189348Abstract: A semiconductor memory device includes a first memory cell, a first select transistor between the first memory cell and a source line, a second select transistor between the first memory cell and a bit line, a third select transistor between the source line and the bit line, and a control circuit. During an erase operation, the control circuit is configured to apply a first voltage to the source line, apply a second voltage lower than the first voltage to a gate of the third select transistor while applying the first voltage to the source line to cause a third voltage to be applied to the bit line, and apply a fourth voltage lower than the third voltage to the gate of the second select transistor while the third voltage is applied to the bit line.Type: GrantFiled: September 1, 2020Date of Patent: November 30, 2021Assignee: KIOXIA CORPORATIONInventors: Takeshi Hioka, Naofumi Abiko, Masaki Unno
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Publication number: 20210233596Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells, a first word line, first and second sense amplifiers, first and second bit lines, a controller. The first and second sense amplifiers each include first and second transistors. The first bit line is connected between the first memory cell and the first transistor. The second bit line is connected between the second memory cell and the second transistor. In the read operation, the controller is configured to apply a kick voltage to the first word line before applying the read voltage to the first word line, and to apply a first voltage to a gate of the first transistor and a second voltage to a gate of the second transistor while applying the kick voltage to the first word line.Type: ApplicationFiled: April 14, 2021Publication date: July 29, 2021Applicant: Toshiba Memory CorporationInventors: Yoshihiko KAMATA, Naofumi ABIKO
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Publication number: 20210225424Abstract: A semiconductor memory device includes a memory cell, a word line connected to the memory cell, a source line connected to the memory cell, a bit line connected to the memory cell, and a control circuit configured to perform a read operation on the memory cell. During the read operation, the control circuit applies to the word line a first voltage, a second voltage greater than the first voltage after applying the first voltage, and a third voltage greater than the first voltage and smaller than the second voltage after applying the second voltage, and applies to the source line a fourth voltage according to a timing at which the second voltage is applied to the word line, a fifth voltage smaller than the fourth voltage after applying the fourth voltage, and a sixth voltage greater than the fifth voltage after applying the fifth voltage.Type: ApplicationFiled: April 5, 2021Publication date: July 22, 2021Inventors: Toshifumi WATANABE, Naofumi ABIKO
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Publication number: 20210202007Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation, and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.Type: ApplicationFiled: March 15, 2021Publication date: July 1, 2021Applicant: Kioxia CorporationInventors: Akio SUGAHARA, Akihiro IMAMOTO, Toshifumi WATANABE, Mami KAKOI, Kohei MASUDA, Masahiro YOSHIHARA, Naofumi ABIKO