Abstract: An air-conditioning apparatus includes configured to, when a cooling operation mode is changed into one of multiple dehumidifying operation modes, select the one of the multiple dehumidifying operation modes on the basis of a value of a sensible heat ratio difference ?SHF that is a difference between a target sensible heat ratio acquired from an indoor temperature detected by an indoor temperature sensor, a target indoor temperature, and target indoor humidity and a theoretical minimum possible sensible heat ratio acquired from enthalpy of an indoor air, enthalpy of blown air from the indoor unit when relative humidity is 100%, and enthalpy of sensible heat.

Abstract: An imaging device includes: a pixel array that has a plurality of pixels disposed according to an oblique pixel arrangement; a first conversion means for performing digital conversion for pixel signals output from pixels in an even column of the pixel array; a second conversion means for performing digital conversion for pixel signals output from pixels in an odd column of the pixel array; and an addition means for adding pixel data output from the first conversion means and the second conversion means, wherein each of the first conversion means and the second conversion means includes a counter having a flip-flop, a first latch circuit, and a second latch circuit.

Abstract: A solid-state imaging apparatus includes a comparison section comparing a pixel signal from a pixel with a ramp signal and outputting a comparison signal. A measurement section starts counting in synchronism with the ramp signal and continues the counting until a signal supplied thereto reverses to measure comparison time. A comparator output controlling section interposed between the output of the comparison section and the input of the measurement section stops, if a pixel signal value exceeds a predetermined value determined based on a tanning phenomenon when the counting is started, the counting when the comparison signal is supplied to the measurement section to reverse the comparison signal, but supplies, if the pixel signal value does not exceed the predetermined value, a signal which is not reversed within a measurement period to the measurement section to continue the counting during the measurement period.

Abstract: An imaging device includes: a pixel array that has a plurality of pixels disposed according to an oblique pixel arrangement; a first conversion means for performing digital conversion for pixel signals output from pixels in an even column of the pixel array; a second conversion means for performing digital conversion for pixel signals output from pixels in an odd column of the pixel array; and an addition means for adding pixel data output from the first conversion means and the second conversion means, wherein each of the first conversion means and the second conversion means includes a counter having a flip-flop, a first latch circuit, and a second latch circuit.

Abstract: A solid-state imaging apparatus includes a comparison section comparing a pixel signal from a pixel with a ramp signal and outputting a comparison signal. A measurement section starts counting in synchronism with the ramp signal and continues the counting until a signal supplied thereto reverses to measure comparison time. A comparator output controlling section interposed between the output of the comparison section and the input of the measurement section stops, if a pixel signal value exceeds a predetermined value determined based on a tanning phenomenon when the counting is started, the counting when the comparison signal is supplied to the measurement section to reverse the comparison signal, but supplies, if the pixel signal value does not exceed the predetermined value, a signal which is not reversed within a measurement period to the measurement section to continue the counting during the measurement period.

Abstract: A solid-state imaging device includes a reference-signal generating unit that generates plural kinds of reference signals for converting an analog pixel signal into digital data, a reference-signal selecting unit that selects any one of the plural kinds of reference signals, a comparing unit that compares the pixel signal and the selected reference signal, and a count unit that performs count processing in parallel with comparison processing in the comparing unit and stores a count value at a point when the comparison processing is completed. The count unit decides digital data of the pixel signal in a 1 LSB step by storing a count value at a point when the comparison processing is completed for any one of the plural kinds of reference signals and correcting the stored count value on the basis of results of the comparison processing for respective remaining reference signals of the plural kinds of reference signals.

Abstract: A memory wherein any “disturb effect” can be suppressed in which data in unselected memory cells are lost. This memory has a memory cell array (1) including bit lines, word lines, which are disposed to intersect the bit lines, and memory cells (12) each connected between bit and word lines. In this memory, an access operation, which includes at least one of read, rewrite and write operations, is made to a selected memory cell (12). During this access operation, it is performed to apply to the memory cell (12) a first voltage pulse, which provides an electrical field in a first direction so as to invert a stored data, and a second voltage pulse, which provides as electrical field in the opposite direction to the first one so as not to invert the stored data. In addition, a recovery operation for recovering a residual polarization amount is made to the memory cell (12).

Abstract: A memory capable of suppressing disturbance causing disappearance of data in a nonselected memory cell is provided. This memory comprises a memory cell array including a bit line, a word line arranged to intersect with the bit line and memory cells connected between the bit line and the word line, for accessing a selected memory cell thereby deteriorating a remanent polarization in an arbitrary memory cell and thereafter performing recovery for recovering all memory cells to remanent polarizations immediately after a write operation or remanent polarizations subjected to single application of a voltage applied to a nonselected memory cell in the access.

Abstract: A solid-state imaging device includes a reference-signal generating unit that generates plural kinds of reference signals for converting an analog pixel signal into digital data, a reference-signal selecting unit that selects any one of the plural kinds of reference signals, a comparing unit that compares the pixel signal and the selected reference signal, and a count unit that performs count processing in parallel with comparison processing in the comparing unit and stores a count value at a point when the comparison processing is completed. The count unit decides digital data of the pixel signal in a 1 LSB step by storing a count value at a point when the comparison processing is completed for any one of the plural kinds of reference signals and correcting the stored count value on the basis of results of the comparison processing for respective remaining reference signals of the plural kinds of reference signals.

Abstract: A memory capable of inhibiting a non-selected cell from disturbance is provided. This memory comprises a bit line, a word line arranged to intersect with the bit line and first storage means connected between the bit line and the word line, for applying voltages of opposite directions to the first storage means of a non-selected memory cell by the same number of times or substantially applying no voltages throughout a read operation and a rewrite operation while varying a rewriting method with a case of reading first data by the read operation and with a case of reading second data by the read operation.

Abstract: A memory capable of suppressing reduction of a reading voltage in data reading regardless of dispersion in a manufacturing process is provided. This memory comprises charge storage means, a first field-effect transistor and data determination means. The memory sets a voltage between a control terminal and a remaining first terminal of the first field-effect transistor to a threshold voltage for bringing the first field-effect transistor into an OFF-state in the vicinity of a boundary state between ON- and OFF-states through the threshold voltage of the first field-effect transistor.

Abstract: A memory wherein any “disturb effect” can be suppressed in which data in unselected memory cells are lost. This memory has a memory cell array(1) including bit lines, word lines, which are disposed to intersect the bit lines, and memory cells(12) each connected between bit and word lines. In this memory, an access operation, which includes at least one of read, rewrite and write operations, is made to a selected memory cell(12). During this access operation, it is performed to apply to the memory cell(12) a first voltage pulse, which provides an electrical field in a first direction so as to invert a stored data, and a second voltage pulse, which provides as electrical field in the opposite direction to the first one so as not to invert the stored data. In addition, a recovery operation for recovering a residual polarization amount is made to the memory cell(12).

Abstract: A memory capable of inhibiting a non-selected cell from disturbance is provided. This memory comprises a bit line, a word line arranged to intersect with the bit line and first storage means connected between the bit line and the word line, for applying voltages of opposite directions to the first storage means of a non-selected memory cell by the same number of times or substantially applying no voltages throughout a read operation and a rewrite operation while varying a rewriting method with a case of reading first data by the read operation and with a case of reading second data by the read operation.

Abstract: A memory capable of easily setting a reference potential and correctly determining data is provided. This memory comprises a ferroelectric capacitor holding data, and a driving line and a data line linked with the ferroelectric capacitor. The memory applies a voltage pulse to the ferroelectric capacitor through the driving line when reading the data thereby generating a negative potential on the data line if the ferroelectric capacitor holds first data, or generating a positive potential on the data line if the ferroelectric capacitor holds second data.

Abstract: A memory capable of suppressing disturbance causing disappearance of data from a nonselected memory cell is provided. This memory applies a second voltage of polarity reverse to that of a first voltage applied to a nonselected memory cell in a read operation to at least the nonselected memory cell in addition to the read operation collectively performed on all memory cells connected to a selected word line.

Abstract: A memory capable of suppressing disturbance is provided. This memory activates each of a selected word line and a bit line corresponding to unrewritten storage means while keeping potential difference therebetween at a level not more than a prescribed value and differentiates the length of a period for applying a voltage for rewriting to each of the selected word line and a bit line corresponding to rewritten storage means from the length of a transition period of the potential of at least either the word line or the bit line corresponding to the unrewritten storage means when performing a rewrite operation on partial selected storage means or performing no rewrite operation on all selected storage means.

Abstract: A memory capable of suppressing reduction of a reading voltage in data reading regardless of dispersion in a manufacturing process is provided. This memory comprises charge storage means, a first field-effect transistor and data determination means. The memory sets a voltage between a control terminal and a remaining first terminal of the first field-effect transistor to a threshold voltage for bringing the first field-effect transistor into an OFF-state in the vicinity of a boundary state between ON- and OFF-states through the threshold voltage of the first field-effect transistor.

Abstract: A memory capable of suppressing disturbance is provided. This memory comprises a bit line, a word line arranged to intersect with the bit line and first storage means connected between the bit line and the word line, and applies prescribed reverse voltages to at least non-selected first storage means connected to a non-selected word line substantially identical times respectively or substantially applies no voltage through a read operation and a rewrite operation.

Abstract: A memory capable of easily setting a reference potential and correctly determining data is provided. This memory comprises a ferroelectric capacitor holding data, and a driving line and a data line linked with the ferroelectric capacitor. The memory applies a voltage pulse to the ferroelectric capacitor through the driving line when reading the data thereby generating a negative potential on the data line if the ferroelectric capacitor holds first data, or generating a positive potential on the data line if the ferroelectric capacitor holds second data.

Abstract: A memory capable of suppressing disturbance is provided. This memory comprises a bit line, a word line arranged to intersect with the bit line and first storage means connected between the bit line and the word line, and applies prescribed reverse voltages to at least non-selected first storage means connected to a non-selected word line substantially identical times respectively or substantially applies no voltage through a read operation and a rewrite operation.