Patents by Inventor Naohide Hamada

Naohide Hamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160343598
    Abstract: A semiconductor device manufacturing method which uses a FOUP capable of suppressing semiconductor substrate defects due to outgas. The FOUP includes: a main body having an opening for taking in or out a semiconductor wafer; a cover detachably attached to the main body in close contact with the main body in a manner to cover the opening; an intake hole and an exhaust hole which are formed in the main body; and a first filter provided on the intake hole and a second filter provided on the exhaust hole. With the semiconductor wafer housed in the internal space of the main body, the FOUP is ventilated by taking external air into the internal space from the intake hole through the first filter and taking the air in the internal space out of the main body from the exhaust hole.
    Type: Application
    Filed: March 28, 2016
    Publication date: November 24, 2016
    Inventors: Jiro SAKAGUCHI, Akira KOIWA, Kaichiro KOBAYASHI, Kenichi SATO, Naohide HAMADA, Nobuaki TOMA
  • Publication number: 20160211146
    Abstract: Manufacturing yield of semiconductor device is improved by suppressing generation of foreign objects in a high-density plasma processing device. A high-density plasma CVD device includes an electrode, a guard ring surrounding an outer circumference of the electrode, an insulating member which is arranged over the guard ring and which surrounds the outer circumference of the electrode, and a plurality of spacers arranged between the guard ring and the insulating member. A height difference between an upper surface of the electrode and an upper surface of the insulating member is set to 0.05 to 0.25 mm.
    Type: Application
    Filed: October 28, 2015
    Publication date: July 21, 2016
    Inventors: Ayaka OKUMURA, Naohide HAMADA
  • Patent number: 6730594
    Abstract: In a method of manufacturing a semiconductor device having a buried wiring structure of copper, a conductive barrier film 17a of buried second layer wirings L2 is protected against oxidation upon forming an insulative film 15b for a wiring cap with an SiON film formed by a plasma CVD method using a gas mixture, for example, of a trimethoxysilane gas and a nitrogen oxidized gas, whereby the dielectric breakdown strength between wirings of copper as the main conductor layer of the semiconductor device can be improved.
    Type: Grant
    Filed: October 25, 2002
    Date of Patent: May 4, 2004
    Assignees: Renesas Technology Corp., Hitachi Tokyo Electronics Co., Ltd.
    Inventors: Junji Noguchi, Naohide Hamada
  • Publication number: 20030087513
    Abstract: Method of manufacturing a semiconductor device having a buried wiring structure comprising copper in which a conductive barrier film 17a of buried second layer wirings L2 is protected against oxidation upon forming an insulative film 15b for wiring cap with an SiON film formed by a plasma CVD method using a gas mixture, for example, of a trimethoxysilane gas and a nitrogen oxidized gas, whereby dielectric break down strength between wirings comprising copper as the main conductor layer of the semiconductor device can be improved.
    Type: Application
    Filed: October 25, 2002
    Publication date: May 8, 2003
    Inventors: Junji Noguchi, Naohide Hamada