Patents by Inventor Naohiko Irle

Naohiko Irle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Indexing branch target instruction memory using target address generated by branch control instruction to reduce branch latency
    Patent number: 6389531
    Abstract: A processor is provided with an improved instruction buffer, branch target instruction memory, branch target address memory and instruction decoder adapted for handling branch instructions so as to reduce latencies. A branch operation uses both a program branch control instruction (executed in advance to determine the branch target instruction address) and either a conditional or unconditional branch instruction associated with a conditional/unconditional branch target instruction respectively. The conditional/unconditional branch instruction and the program branch control instruction both include separate prediction indicators used by the instruction decoder for initiating a loading and speculatively pre-loading of instructions for execution in the processor.
    Type: Grant
    Filed: October 17, 2000
    Date of Patent: May 14, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Naohiko Irle, Tony Lee Werner