Abstract: In a semiconductor substrate having a silicon carbide substrate and an epitaxial film, a concentration ratio between a hydrogen concentration in the silicon carbide substrate and a hydrogen concentration in the epitaxial film is in a range between 0.2 and 5, preferably in a range between 0.5 and 2. Thus, hydrogen diffusion at a boundary position between the epitaxial film and the SiC substrate is restricted. Further, it is possible to prepare the semiconductor substrate for restricting the reduction of the hydrogen concentration. Thus, it is possible to improve the properties of the SiC semiconductor device using the semiconductor substrate, for example, the bipolar device such as a PN diode.

Abstract: In a semiconductor substrate having a silicon carbide substrate and an epitaxial film, a concentration ratio between a hydrogen concentration in the silicon carbide substrate and a hydrogen concentration in the epitaxial film is in a range between 0.2 and 5, preferably in a range between 0.5 and 2. Thus, hydrogen diffusion at a boundary position between the epitaxial film and the SiC substrate is restricted. Further, it is possible to prepare the semiconductor substrate for restricting the reduction of the hydrogen concentration. Thus, it is possible to improve the properties of the SiC semiconductor device using the semiconductor substrate, for example, the bipolar device such as a PN diode.

Abstract: In a method for manufacturing a silicon carbide semiconductor device having a JFET, a trench is formed in a semiconductor substrate, and a channel layer and a second gate region are formed on an inner wall of the trench. The channel layer and the second gate region are planarized to expose a source region. A first recess deeper than a thickness of the source region is formed on both leading ends of the trench, and an activation annealing process of 1300° C. or higher is conducted in an inert gas atmosphere. A first conductivity type layer formed by the annealing process to cover a corner which is a boundary between a bottom and a side of the first recess is removed.

Abstract: In a method of manufacturing a silicon carbide semiconductor device having a JFET, after forming a second concave portion configuring a second mesa portion, a thickness of a source region is detected by observing a pn junction between the source region and a first gate region exposed by the second concave portion. Selective etching is conducted on the basis of the detection result to form a first concave portion deeper than the thickness of the source region and configuring a first mesa portion inside of an outer peripheral region in an outer periphery of a cell region, and to make the second concave portion deeper than the second gate region.

Abstract: In a method for manufacturing a silicon carbide semiconductor device having a JFET, a trench is formed in a semiconductor substrate, and a channel layer and a second gate region are formed on an inner wall of the trench. The channel layer and the second gate region are planarized to expose a source region. A first recess deeper than a thickness of the source region is formed on both leading ends of the trench, and an activation annealing process of 1300° C. or higher is conducted in an inert gas atmosphere. A first conductivity type layer formed by the annealing process to cover a corner which is a boundary between a bottom and a side of the first recess is removed.

Abstract: In a method of manufacturing a silicon carbide semiconductor device having a JFET, after forming a second concave portion configuring a second mesa portion, a thickness of a source region is detected by observing a pn junction between the source region and a first gate region exposed by the second concave portion. Selective etching is conducted on the basis of the detection result to form a first concave portion deeper than the thickness of the source region and configuring a first mesa portion inside of an outer peripheral region in an outer periphery of a cell region, and to make the second concave portion deeper than the second gate region.

Abstract: A wide band gap semiconductor device having a JFET, a MESFET, or a MOSFET mainly includes a semiconductor substrate, a first conductivity type semiconductor layer, and a first conductivity type channel layer. The semiconductor layer is formed on a main surface of the substrate. A recess is formed in the semiconductor layer in such a manner that the semiconductor layer is divided into a source region and a drain region. The recess has a bottom defined by the main surface of the substrate and a side wall defined by the semiconductor layer. The channel layer has an impurity concentration lower than an impurity concentration of the semiconductor layer. The channel layer is formed on the bottom and the side wall of the recess by epitaxial growth.

Abstract: A silicon carbide semiconductor device having a JFET or a MOSFET includes a semiconductor substrate and a trench. The semiconductor substrate has a silicon carbide substrate, a drift layer on the silicon carbide substrate, a first gate region on the drift layer, and a source region on the first gate region. The trench has a strip shape with a longitudinal direction and reaches the drift layer by penetrating the source region and the first gate region. The trench is filled with a channel layer and a second gate region on the channel layer. The source region is not located at an end portion of the trench in the longitudinal direction.

Abstract: A semiconductor device includes: a substrate; and depletion and enhancement mode JFETs. The depletion mode JFET includes: a concavity on the substrate; a channel layer in the concavity; a first gate region on the channel layer; first source and drain regions on respective sides of the first gate region in the channel layer; first gate, source and drain electrodes. The enhancement mode JFET includes: a convexity on the substrate; the channel layer on the convexity; a second gate region on the channel layer; second source and drain regions on respective sides of the second gate region in the channel layer; second gate, source and drain electrodes. A thickness of the channel layer in the concavity is larger than a thickness of the channel layer on the convexity.

Abstract: A ceramic material has a perovskite structure and is represented by formula of (1?x)ABO3-xYZO3. In the formula, “x” is a real number that is greater than 0 and is less than 1 each of “A,” “B,” “Y,” and “Z” is one or more kinds selected from a plurality of metal ions M other than a Pb ion and alkali metal ions, “A” is bivalent, “B” is tetravalent, “Y” is trivalent or combination of trivalent metal ions, and “Z” is bivalent and/or trivalent metal ions, or a bivalent and/or pentavalent metal ions.

Abstract: A semiconductor device includes: a substrate; and depletion and enhancement mode JFETs. The depletion mode JFET includes: a concavity on the substrate; a channel layer in the concavity; a first gate region on the channel layer; first source and drain regions on respective sides of the first gate region in the channel layer; first gate, source and drain electrodes. The enhancement mode JFET includes: a convexity on the substrate; the channel layer on the convexity; a second gate region on the channel layer; second source and drain regions on respective sides of the second gate region in the channel layer; second gate, source and drain electrodes. A thickness of the channel layer in the concavity is larger than a thickness of the channel layer on the convexity.

Abstract: A semiconductor device having a JFET includes: a substrate made of semi-insulating semiconductor material; a gate region in a surface portion of the substrate; a channel region disposed on and contacting the gate region; a source region and a drain region disposed on both sides of the gate region so as to sandwich the channel region, respectively; a source electrode electrically coupled with the source region; a drain electrode electrically coupled with the drain region; and a gate electrode electrically coupled with the gate region. An impurity concentration of each of the source region and the drain region is higher than an impurity concentration of the channel region.

Abstract: A silicon carbide semiconductor device having a JFET or a MOSFET includes a semiconductor substrate and a trench. The semiconductor substrate has a silicon carbide substrate, a drift layer on the silicon carbide substrate, a first gate region on the drift layer, and a source region on the first gate region. The trench has a strip shape with a longitudinal direction and reaches the drift layer by penetrating the source region and the first gate region. The trench is filled with a channel layer and a second gate region on the channel layer. The source region is not located at an end portion of the trench in the longitudinal direction.

Abstract: A wide band gap semiconductor device having a JFET, a MESFET, or a MOSFET mainly includes a semiconductor substrate, a first conductivity type semiconductor layer, and a first conductivity type channel layer. The semiconductor layer is formed on a main surface of the substrate. A recess is formed in the semiconductor layer in such a manner that the semiconductor layer is divided into a source region and a drain region. The recess has a bottom defined by the main surface of the substrate and a side wall defined by the semiconductor layer. The channel layer has an impurity concentration lower than an impurity concentration of the semiconductor layer. The channel layer is formed on the bottom and the side wall of the recess by epitaxial growth.

Abstract: A ceramic material has a perovskite structure and is represented by formula of (1?x)ABO3-xYZO3. In the formula, “x” is a real number that is greater than 0 and is less than 1 each of “A,” “B,” “Y,” and “Z” is one or more kinds selected from a plurality of metal ions M other than a Pb ion and alkali metal ions, “A” is bivalent, “B” is tetravalent, “Y” is trivalent or combination of trivalent metal ions, and “Z” is bivalent and/or trivalent metal ions, or a bivalent and/or pentavalent metal ions.

Abstract: A method for manufacturing a silicon carbide single crystal includes the steps of: setting a substrate as a seed crystal in a reactive chamber; introducing a raw material gas into the reactive chamber; growing a silicon carbide single crystal from the substrate; heating the gas at an upstream side from the substrate in a gas flow path; keeping a temperature of the substrate at a predetermined temperature lower than the gas so that the single crystal is grown from the substrate; heating a part of the gas, which is a non-reacted raw material gas and does not contribute to crystal growth, after passing through the substrate; and absorbing a non-reacted raw material gas component in the non-reacted raw material gas with an absorber.

Abstract: A method for manufacturing a silicon carbide single crystal includes the steps of: preparing a seed crystal with a screw dislocation generation region; and growing the single crystal on a growth surface of the seed crystal. The generation region occupies equal to or smaller than 50% of the growth surface, which has an offset angle equal to or smaller than 60 degrees. The screw dislocation density in the single crystal generated from the generation region is higher than that in the other region. The single crystal includes a flat C-surface facet disposed on a growing surface of the single crystal. The C-surface facet overlaps at least one of parts of the growing surface provided by projecting the generation region in a direction perpendicular to the growth surface and in a direction parallel to a <0001> axis, respectively.

Abstract: A method for manufacturing a silicon carbide single crystal includes the steps of: preparing a seed crystal with a screw dislocation generation region; and growing the single crystal on a growth surface of the seed crystal. The generation region occupies equal to or smaller than 50% of the growth surface, which has an offset angle equal to or smaller than 60 degrees. The screw dislocation density in the single crystal generated from the generation region is higher than that in the other region. The single crystal includes a flat C-surface facet disposed on a growing surface of the single crystal. The C-surface facet overlaps at least one of parts of the growing surface provided by projecting the generation region in a direction perpendicular to the growth surface and in a direction parallel to a <0001> axis, respectively.

Abstract: A method for manufacturing a silicon carbide single crystal includes the steps of: setting a substrate as a seed crystal in a reactive chamber; introducing a raw material gas into the reactive chamber; growing a silicon carbide single crystal from the substrate; heating the gas at an upstream side from the substrate in a gas flow path; keeping a temperature of the substrate at a predetermined temperature lower than the gas so that the single crystal is grown from the substrate; heating a part of the gas, which is a non-reacted raw material gas and does not contribute to crystal growth, after passing through the substrate; and absorbing a non-reacted raw material gas component in the non-reacted raw material gas with an absorber.

Abstract: It is the purpose of the present invention to prevent a macroscopic defect in the production of an SiC single crystal. SiC source material powder and an SiC seed crystal are disposed inside a graphite crucible, and the SiC source material powder is thermally sublimated and recrystallized on a front surface of the SiC seed crystal to grow an SiC single crystal. In this sublimation-recrystallization method, a protection layer is provided on a back surface of the SiC seed crystal. The SiC seed crystal is mechanically supported by a supporting part disposed on the graphite crucible without bonding. Thereby, it is possible to improve the thermal maldistribution on the back surface of the SiC seed crystal and possible to suppress damage of the protection layer due to the thermal maldistribution. Thus, macroscopic defects in the grown SiC single crystal are preferably suppressed.