Patents by Inventor Naohiro Takazawa

Naohiro Takazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240307127
    Abstract: A processing apparatus includes a processor. The processor acquires an image in which region marker information of a lesion is set with respect to an ultrasonic image of an ultrasonic endoscope with a biopsy needle, and calculates an angle of the biopsy needle for inserting the biopsy needle into the lesion based on a movable range of the biopsy needle and the region marker information.
    Type: Application
    Filed: March 15, 2024
    Publication date: September 19, 2024
    Applicant: OLYMPUS CORPORATION
    Inventors: Genri INAGAKI, Naohiro TAKAZAWA, Ryohei OGAWA, Masamichi MIDORIKAWA, Hidetoshi NISHIMURA, Jordan MILFORD, Hirokazu HORIO, Hiroyuki MINO
  • Patent number: 10607942
    Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer, a first pad, and a second pad. A first opening and a second opening are formed in a first main surface of the first semiconductor layer. The second semiconductor layer is stacked on the first semiconductor layer. The first pad for wire bonding is disposed in the first opening. The second pad on which an alignment mark is formed is disposed in the second opening. A third opening and a fourth opening penetrate the second semiconductor layer. The first opening overlaps the third opening. The second opening overlaps the fourth opening.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: March 31, 2020
    Assignee: OLYMPUS CORPORATION
    Inventor: Naohiro Takazawa
  • Patent number: 10566292
    Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer, a first pad, and a second pad. A first opening and a second opening are formed in a first main surface of the first semiconductor layer. The second semiconductor layer is stacked on the first semiconductor layer. The first pad for wire bonding is disposed in the first opening. The second pad on which an alignment mark is formed is disposed in the second opening. A third opening and a fourth opening penetrate the second semiconductor layer. The first opening overlaps the third opening. The second opening overlaps the fourth opening.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: February 18, 2020
    Assignee: OLYMPUS CORPORATION
    Inventor: Naohiro Takazawa
  • Publication number: 20180366414
    Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer, a first pad, and a second pad. A first opening and a second opening are formed in a first main surface of the first semiconductor layer. The second semiconductor layer is stacked on the first semiconductor layer. The first pad for wire bonding is disposed in the first opening. The second pad on which an alignment mark is formed is disposed in the second opening. A third opening and a fourth opening penetrate the second semiconductor layer. The first opening overlaps the third opening. The second opening overlaps the fourth opening.
    Type: Application
    Filed: August 28, 2018
    Publication date: December 20, 2018
    Applicant: OLYMPUS CORPORATION
    Inventor: Naohiro Takazawa
  • Patent number: 9978723
    Abstract: A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a bonding electrode, and a dummy electrode. The first semiconductor substrate has a first surface and a first wiring, and contains a first semiconductor material. The second semiconductor substrate has a second surface and a second wiring, and contains a second semiconductor material, and the first surface and the second surface face each other. The bonding electrode is arranged between the first surface and the second surface, and is electrically connected to the first wiring and the second wiring. The dummy electrode is arranged between the first surface and the second surface, and is electrically insulated from at least one of the first wiring and the second wiring. The bonding electrode has a bonding bump and a first bonding pad. The dummy electrode has a dummy bump and a first dummy pad.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: May 22, 2018
    Assignee: OLYMPUS CORPORATION
    Inventors: Naohiro Takazawa, Yoshitaka Tadaki
  • Publication number: 20180061779
    Abstract: A semiconductor device includes a first substrate, a second substrate, a first pad, a second pad, a first micro-bump, a first resin layer, and an insulating layer. The first substrate has a first semiconductor layer and a first wire layer. The second substrate has a second semiconductor layer and a second wire layer. The insulating layer contains an insulating material having hygroscopic properties lower than hygroscopic properties of the first resin layer. The insulating layer penetrates the second substrate and the first resin layer. The insulating layer surrounds the first micro-bump in a first cross section which passes through the first micro-bump, the first resin layer, and the insulating layer and is parallel to the first surface.
    Type: Application
    Filed: November 2, 2017
    Publication date: March 1, 2018
    Applicant: OLYMPUS CORPORATION
    Inventors: Naohiro Takazawa, Yoshitaka Tadaki
  • Publication number: 20170309599
    Abstract: A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a bonding electrode, and a dummy electrode. The first semiconductor substrate has a first surface and a first wiring, and contains a first semiconductor material. The second semiconductor substrate has a second surface and a second wiring, and contains a second semiconductor material, and the first surface and the second surface face each other. The bonding electrode is arranged between the first surface and the second surface, and is electrically connected to the first wiring and the second wiring. The dummy electrode is arranged between the first surface and the second surface, and is electrically insulated from at least one of the first wiring and the second wiring. The bonding electrode has a bonding bump and a first bonding pad. The dummy electrode has a dummy bump and a first dummy pad.
    Type: Application
    Filed: July 7, 2017
    Publication date: October 26, 2017
    Applicant: OLYMPUS CORPORATION
    Inventors: Naohiro Takazawa, Yoshitaka Tadaki
  • Patent number: 9716069
    Abstract: A semiconductor substrate includes: an alignment mark being formed of a material that reflects a detection light for detecting positions and having a detection edge portion; a light-shielding layer portion having a larger outer shape than the alignment mark, being formed of a material that shields the detection light, and being disposed at a position on a backside of the alignment mark when seen from an incidence side of the detection light; and one or more light-transmitting layer portions being laminated between the alignment mark and the light-shielding layer portion so as to transmit the detection light and not being patterned at least in a range that overlaps the light-shielding layer portion.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: July 25, 2017
    Assignee: OLYMPUS CORPORATION
    Inventors: Naohiro Takazawa, Yoshiaki Takemoto
  • Patent number: 9478520
    Abstract: A solid-state imaging device is a solid-state imaging device in which a first substrate formed on a first semiconductor wafer and a second substrate formed on a second semiconductor wafer are bonded via connect that electrically connects the substrates, wherein the first substrate includes photoelectric conversion units, the second substrate includes an output circuit that acquires a signal generated by the photoelectric conversion unit via the connector and outputs the signal, and dummy connectors that support the first and second bonded substrates are further arranged in a substrate region in which the connectors are not arranged in a substrate region of at least one of the first substrate and the second substrate.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: October 25, 2016
    Assignee: OLYMPUS CORPORATION
    Inventors: Mitsuhiro Tsukimura, Naohiro Takazawa, Yoshiaki Takemoto, Hiroshi Kikuchi, Haruhisa Saito, Yoshitaka Tadaki, Yuichi Gomi
  • Publication number: 20160284754
    Abstract: A semiconductor device includes a plurality of substrates including a semiconductor layer and a wiring layer, wherein each of the plurality of substrates is separated from and overlap other substrate of the plurality of substrates in a direction crossing a main surface, and the wiring layer of an edge substrate is arranged between the semiconductor layer of the edge substrate and the substrate adjacent to the edge substrate, a connection portion that electrically connects two adjacent substrates among the plurality of substrates, a resin layer that is arranged between the two adjacent substrates among the plurality of substrates, and a first opening portion that is formed in the semiconductor layer of the edge substrate, the shape of the first opening portion viewed in the direction squarely facing the main surface of the edge substrate being a polygon having five or more sides or a circle.
    Type: Application
    Filed: June 3, 2016
    Publication date: September 29, 2016
    Applicant: OLYMPUS CORPORATION
    Inventor: Naohiro Takazawa
  • Publication number: 20150348914
    Abstract: A semiconductor substrate includes: an alignment mark being formed of a material that reflects a detection light for detecting positions and having a detection edge portion; a light-shielding layer portion having a larger outer shape than the alignment mark, being formed of a material that shields the detection light, and being disposed at a position on a backside of the alignment mark when seen from an incidence side of the detection light; and one or more light-transmitting layer portions being laminated between the alignment mark and the light-shielding layer portion so as to transmit the detection light and not being patterned at least in a range that overlaps the light-shielding layer portion.
    Type: Application
    Filed: August 10, 2015
    Publication date: December 3, 2015
    Applicant: OLYMPUS CORPORATION
    Inventors: Naohiro Takazawa, Yoshiaki Takemoto
  • Publication number: 20150340400
    Abstract: A stacked solid-state imaging device includes a first substrate and a second substrate that are stacked on each other, a photoelectric conversion unit that converts incident light into an electrical signal, an electrode portion that is provided on the first substrate and has an exposed surface exposed to the outside in order to deliver an electrical signal to and from the outside, a connection portion that electrically connects a first contact portion provided on the first substrate and a second contact portion provided on the second substrate, and a wiring portion that is provided on the first substrate and electrically connects the electrode portion and the first contact portion in which the connection portion is arranged so as not to overlap the exposed surface when seen from a stacked direction in which the first substrate and the second substrate are stacked on each other.
    Type: Application
    Filed: August 4, 2015
    Publication date: November 26, 2015
    Applicant: OLYMPUS CORPORATION
    Inventors: Yoshiaki Takemoto, Mitsuhiro Tsukimura, Naohiro Takazawa
  • Publication number: 20150008593
    Abstract: A stacked semiconductor device includes a first substrate and a second substrate. The first electrode is connected to the second electrode so that the first surface faces the second surface. A tip portion of the first wall section that faces the second substrate is connected to a tip portion of the second wall section that faces the first substrate. The first wall section is connected to the second wall section over an entire circumference. An outside space that is formed in an outside of the first wall section and an outside of the second wall section between the first substrate and the second substrate is filled with a sealing member over the entire circumference.
    Type: Application
    Filed: September 19, 2014
    Publication date: January 8, 2015
    Applicant: OLYMPUS CORPORATION
    Inventors: Yoshiaki Takemoto, Naohiro Takazawa, Hiroshi Kikuchi
  • Publication number: 20140367853
    Abstract: A solid-state imaging device is a solid-state imaging device in which a first substrate formed on a first semiconductor wafer and a second substrate formed on a second semiconductor wafer are bonded via connect that electrically connects the substrates, wherein the first substrate includes photoelectric conversion units, the second substrate includes an output circuit that acquires a signal generated by the photoelectric conversion unit via the connector and outputs the signal, and dummy connectors that support the first and second bonded substrates are further arranged in a substrate region in which the connectors are not arranged in a substrate region of at least one of the first substrate and the second substrate.
    Type: Application
    Filed: August 27, 2014
    Publication date: December 18, 2014
    Applicant: OLYMPUS CORPORATION
    Inventors: Mitsuhiro Tsukimura, Naohiro Takazawa, Yoshiaki Takemoto, Hiroshi Kikuchi, Haruhisa Saito, Yoshitaka Tadaki, Yuichi Gomi
  • Patent number: 8847296
    Abstract: A solid-state imaging device is a solid-state imaging device in which a first substrate formed on a first semiconductor wafer and a second substrate formed on a second semiconductor wafer are bonded via connect that electrically connects the substrates, wherein the first substrate includes photoelectric conversion units, the second substrate includes an output circuit that acquires a signal generated by the photoelectric conversion unit via the connector and outputs the signal, and dummy connectors that support the first and second bonded substrates are further arranged in a substrate region in which the connectors are not arranged in a substrate region of at least one of the first substrate and the second substrate.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: September 30, 2014
    Assignee: Olympus Corporation
    Inventors: Mitsuhiro Tsukimura, Naohiro Takazawa, Yoshiaki Takemoto, Hiroshi Kikuchi, Haruhisa Saito, Yoshitaka Tadaki, Yuichi Gomi
  • Patent number: D641048
    Type: Grant
    Filed: January 20, 2010
    Date of Patent: July 5, 2011
    Assignee: Kabushiki Kaisha Sega
    Inventors: Hiroki Nunokawa, Mari Fujisawa, Naohiro Takazawa, Yuki Hanafusa, Yuji Sugimori