Patents by Inventor Naohisa Toda

Naohisa Toda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7713851
    Abstract: A silicon epitaxial layer 2 is grown in vapor phase on a silicon single crystal substrate 1 manufactured by the Czochralski method, and doped with boron so as to adjust the resistivity to 0.02 ?·cm or below, oxygen precipitation nuclei 11 are formed in the silicon single crystal substrate 1, by carrying out annealing at 450° C. to 750° C., in an oxidizing atmosphere, for a duration of time allowing formation of a silicon oxide film only to as thick as 2 nm or below on the silicon epitaxial layer 2 as a result of the annealing, and thus-formed silicon oxide film 3 is etched as the first cleaning after the low-temperature annealing, using a cleaning solution. By this process, the final residual thickness of the silicon oxide film can be suppressed only to a level equivalent to native oxide film, without relying upon the hydrofluoric acid cleaning.
    Type: Grant
    Filed: August 3, 2005
    Date of Patent: May 11, 2010
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Fumitaka Kume, Tomosuke Yoshida, Ken Aihara, Ryoji Hoshi, Satoshi Tobe, Naohisa Toda, Fumio Tahara
  • Publication number: 20090038540
    Abstract: In a vapor phase growth apparatus, epitaxial growth is performed with respect to a wafer having a CVD film formed on a back surface thereof as a wafer for monitoring that is used to guarantee a resistance and/or measure a thickness of an epitaxial layer, then epitaxial growth is performed with respect to a wafer as a dummy or a vapor phase growth apparatus is activated under conditions for performing epitaxial growth without using a wafer, and subsequently epitaxial growth is carried out with respect to a wafer as a product, thereby manufacturing an epitaxial wafer. As a result, when using a wafer having no CVD film to manufacture an epitaxial wafer that is used to fabricate an imaging device, e.g., a CCD or a CMOS image sensor, a method capable of effectively avoiding heavy-metal contamination and manufacturing a high-quality epitaxial layer is provided.
    Type: Application
    Filed: August 21, 2006
    Publication date: February 12, 2009
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Tomosuke Yoshida, Naohisa Toda
  • Publication number: 20080038526
    Abstract: A silicon epitaxial wafer 100 formed by growing a silicon epitaxial layer 2 on a silicon single crystal substrate 1, produced by a CZ method, and doped with boron so that a resistivity thereof is in the range of 0.009 ?·cm or higher and 0.012 ?·cm or lower. The silicon single crystal substrate 1 has a density of the oxygen precipitation nuclei of 1×1010 cm?3 or higher. A width of a no-oxygen-precipitation-nucleus-forming-region 15, formed between the silicon epitaxial layer 2 and the silicon single substrate 1, is in the range of more than 0 ?m and less than 10 ?m. Thereby, provided is a silicon epitaxial wafer using a boron doped p+ CZ substrate, wherein a formed width of no-oxygen-precipitation-nucleus-forming-region is reduced sufficiently, and oxygen precipitates can be formed having a density sufficient enough to exert an IG effect.
    Type: Application
    Filed: July 5, 2005
    Publication date: February 14, 2008
    Applicant: Shin-Etsu Handotai Co., Ltd.
    Inventors: Fumitaka Kume, Tomosuke Yushida, Ken Aihara, Ryoji Hoshi, Satoshi Tobe, Naohisa Toda, Fumio Tahara
  • Publication number: 20070269338
    Abstract: A silicon epitaxial wafer 100 is formed by growing a silicon epitaxial layer 2 on a silicon single crystal substrate 1, produced by means of a CZ method, and doped with boron so that a resistivity thereof is less than 0.018 ?·cm. The silicon single crystal substrate 1 has a density of bulk stacking faults 13 in the silicon single crystal substrate 1 in the range of 1×108 cm?3 or higher and 3×109 cm?3 or lower. Thereby, provided is a silicon epitaxial wafer having a boron doped p+ CZ substrate with a resistivity of 0.018?·cm or lower, and a state of formation of oxygen precipitates can be adjusted adequately so as to secure a sufficient IG effect and to suppress a problem of bow and deformation of a substrate, despite that sizes of oxygen precipitates is so small to be observed accurately.
    Type: Application
    Filed: June 27, 2005
    Publication date: November 22, 2007
    Applicant: Shin-Etsu Handotai Co., Ltd
    Inventors: Fumitaka Kume, Tomosuke Yoshida, Ken Aihara, Ryoji Hoshi, Satoshi Tobe, Naohisa Toda, Fumio Tahara
  • Publication number: 20070243699
    Abstract: A silicon epitaxial layer 2 is grown in vapor phase on a silicon single crystal substrate 1 manufactured by the Czochralski method, and doped with boron so as to adjust the resistivity to 0.02 ?·cm or below, oxygen precipitation nuclei 11 are formed in the silicon single crystal substrate 1, by carrying out annealing at 450° C. to 750° C., in an oxidizing atmosphere, for a duration of time allowing formation of a silicon oxide film only to as thick as 2 nm or below on the silicon epitaxial layer 2 as a result of the annealing, and thus-formed silicon oxide film 3 is etched as the first cleaning after the low-temperature annealing, using a cleaning solution. By this process, the final residual thickness of the silicon oxide film can be suppressed only to a level equivalent to native oxide film, without relying upon the hydrofluoric acid cleaning.
    Type: Application
    Filed: August 3, 2005
    Publication date: October 18, 2007
    Applicant: Shin-Etsu Handotai Co., Ltd.
    Inventors: Fumitaka Kume, Tomosuke Yoshida, Ken Aihara, Ryoji Hoshi, Satoshi Tobe, Naohisa Toda, Fumio Tahara
  • Patent number: 6072164
    Abstract: There is provided a heat-treating method and a radiant heating device by which an object to be heat-treated can be heat-treated at an actually desired temperature regardless of the dopant concentration or resistivity of the object at the time of heat-treating the object with a radiant heating device using a radiation thermometer as a temperature detector. In the method, the object is heat-treated at an actually desired temperature by correcting the temperature of the object in accordance with the dopant concentration or resistivity of the object. In the apparatus, the dopant concentration or resistivity of the object is inputted in advance to a temperature controller and the controller calculates an actual temperature of the object by correcting and computing the temperature of the object detected with the radiation thermometer in accordance with the dopant concentration or resistivity of the object and controls the temperature of the object based on the calculated temperature value.
    Type: Grant
    Filed: September 11, 1998
    Date of Patent: June 6, 2000
    Assignee: Shin-Estu Handotai Co., Ltd.
    Inventors: Naoto Tate, Tomoyuki Sakai, Naohisa Toda, Hitoshi Habuka