Patents by Inventor Naohito Asari

Naohito Asari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6849952
    Abstract: A non-lead type, stacked-type semiconductor device includes a sealing body of insulative resin, a tab, leads, each having one surface exposed on a mounting surface of the sealing body, a first semiconductor chip located in the sealing body having a first circuit-forming surface and a second surface supported on the tab through adhesive, electrode pads formed in the periphery of the first surface, conductive wires for electrically connecting the electrode pads and the leads, a second semiconductor chip having a first circuit-forming surface and a second surface opposite to the first surface, and stacked and mounted on the first surface of the first semiconductor chip toward the second surface thereof, electrode pads formed on the first surface of the second semiconductor chip, and conductive wires for electrically connecting the electrode pads of the second semiconductor chip and the leads.
    Type: Grant
    Filed: April 17, 2003
    Date of Patent: February 1, 2005
    Assignees: Renesas Technology Corp., Renesas Northern Japan Semiconductor, Inc.
    Inventors: Hiroki Ishimura, Katsunori Takahashi, Mitsuru Sakamoto, Naohito Asari
  • Publication number: 20040021231
    Abstract: A stacked type semiconductor device, complying with reductions in a mounting height and a mounting area and weight thereof, is realized with high-performance and at low cost using an existing production line.
    Type: Application
    Filed: April 17, 2003
    Publication date: February 5, 2004
    Inventors: Hiroki Ishimura, Katsunori Takahashi, Mitsuru Sakamoto, Naohito Asari