Abstract: According to one embodiment, a circuit design device includes a classification unit and a generation unit. The classification unit is configured to classify a plurality of wires included in a circuit into a first wire group that includes at least one first wire and a second wire group that includes at least one second wire based on toggle rates of the plurality of wires. The generation unit is configured to generate, based on first information indicating a layout of the plurality of wires on a substrate, second information indicating a layout of the plurality of wires on the substrate and a first dummy wire, the first dummy wire being arranged in a first region within a first range from the first wire.

Abstract: According to one embodiment, a design apparatus includes a voltage drop analyzer, an improvement calculator, first and second cell replacing modules, and an outputting module. The voltage drop analyzer specifies a peak voltage drop point based on a cell library and design data. The cell library includes information on first and cell groups. The first cell replacing module changes the design data. The improvement calculator calculates a timing improvement. The second cell replacing module extracts at least one cell from second cell group in a target device corresponding to the design data changed by the first cell replacing module as a replacement candidate cell, based on the timing improvement, and changes the design data changed by the first cell replacing module. The outputting module outputs the design data changed by the second cell replacing module.

Abstract: A semiconductor integrated circuit includes a function block arranged on a substrate, a first buffering cell arranged adjacent to a first side of the function block, a second buffering cell arranged adjacent to a second side adjacent to the first side of the function block, and signal wiring passing over the function block obliquely relative to the first side and the second side, connecting the first buffering cell and the second buffering cell.

Abstract: A semiconductor integrated circuit includes a function block arranged on a substrate, a first buffering cell arranged adjacent to a first side of the function block, a second buffering cell arranged adjacent to a second side adjacent to the first side of the function block, and signal wiring passing over the function block obliquely relative to the first side and the second side, connecting the first buffering cell and the second buffering cell.

Abstract: A method for distributing clocks to flip-flop circuits which constitute a logic circuit includes obtaining a timing slack of a first minimum delay time with respect to a minimum delay constraint time and a timing slack of a first maximum delay time with respect to a maximum delay constraint time for a clock in an input path to a flip-flop circuit, obtaining a timing slack of a second minimum delay time with respect to a minimum delay constraint time and a timing slack of a second maximum delay time with respect to a maximum delay constraint time for a clock in an output path from all the flip-flop circuits which receive the clocks from a clock terminal directly and obtaining a delay value which maximizes a minimum value of each of the first and second minimum delay time and maximum delay time of timing slacks.

Abstract: A semiconductor integrated circuit includes a function block arranged on a substrate, a first buffering cell arranged adjacent to a first side of the function block, a second buffering cell arranged adjacent to a second side adjacent to the first side of the function block, and signal wiring passing over the function block obliquely relative to the first side and the second side, connecting the first buffering cell and the second buffering cell.

Abstract: A repeater insertion method is described which allows for repeater cell insertion into two or more fanout nets. Repeater cell location is determined such that at any given point, the interval capacitance between any two repeater cell nodes is no greater than a predetermined amount. Furthermore, the method allows for successful “back-annotation” into synthesis or layout software without the need to add new input/output pins to the module definition. Additionally, the method allows for repeater cell insertion using two or more sizes of repeater cells. Finally, the method described considers the “slack” of each fanout, and makes the signal delay from the source to the most critical fanout shorter than the result of usual repeater insertion methods.

Abstract: A method for distributing clocks to flip-flop circuits which constitute a logic circuit includes obtaining a timing slack of a first minimum delay time with respect to a minimum delay constraint time and a timing slack of a first maximum delay time with respect to a maximum delay constraint time for a clock in an input path to a flip-flop circuit, obtaining a timing slack of a second minimum delay time with respect to a minimum delay constraint time and a timing slack of a second maximum delay time with respect to a maximum delay constraint time for a clock in an output path from all the flip-flop circuits which receive the clocks from a clock terminal directly and obtaining a delay value which maximizes a minimum value of each of the first and second minimum delay time and maximum delay time of timing slacks.

Abstract: A sizing apparatus for active devices of an integrated circuit has a storage unit for storing information about connections between the active devices and a delay constraint, a size initializing unit for initializing a size of the active device to a minimum value, an electric current consumption change rate arithmetic unit for calculating a change rate of an electric current or power consumption when the size is increased, a delay calculating unit for calculating a maximum signal delay by analyzing a timing on the basis of the connecting formation, a delay constraint judging unit for judging whether or not a maximum signal delay satisfies the delay constraint, a critical path extracting unit for extracting a critical path from paths that do not satisfy the delay constraint, a delay improvement arithmetic unit for calculating an improvement rate of the signal delay of the critical path with respect to a variation quantity of the electric current or power consumption when increasing the size of the active devic