Abstract: The disclosure provides a semiconductor storage device that realizes high integration and improves reliability. A bit line selection circuit (100) of a flash memory includes transistors (BLSeO, BLSeE, BLSoO, BLSoE) in the column direction of bit lines (BL0-BL3), selecting a bit line pair composed of an even-numbered bit line (BL0) and an odd-numbered bit line (BL3) is selected by the transistors, in which a bit line pair (BL1, BL2) adjacent to the selected bit line pair is set as a non-selected bit line pair, and the selected bit line pair (BL0, BL3) is connected to page buffer/sensing circuit through an output node (BLS0, BLS1).

Abstract: A semiconductor memory device including a substrate having a first region and a second region; a plurality of first transistors provided in the first region; a plurality of second transistors provided in the second region, the plurality of second transistors being electrically coupled to the plurality of first transistors, respectively, and a breakdown-voltage of the second transistor being lower than a breakdown-voltage of the first transistor. A plurality of joint metals are provided above the first region, the plurality of joint metals being electrically coupled to the plurality of first transistors, respectively. A plurality of bit lines are provided in an upper layer of the plurality of joint metals, the plurality of bit lines being coupled to the plurality of joint metals, respectively; and a plurality of memory cells are provided in an upper layer of the plurality of bit lines, the plurality of memory cells being coupled to the plurality of bit lines, respectively.

Abstract: A semiconductor memory device according to an embodiment includes a memory chip and a circuit chip. The memory chip includes first and second joint metals. The circuit chip includes first and second sense amplifiers, and third and fourth joint metals facing the first and second joint metals, respectively. The first sense amplifier includes first and second active regions. The first active region includes a first transistor coupled between the third joint metal and the second active region. The second amplifier includes third and fourth active region. The third active region includes a second transistor coupled between the fourth joint metal and the fourth active region. The third and fourth joint metals overlap the first and third active regions, respectively.

Abstract: The disclosure provides a semiconductor storage device that realizes high integration and improves reliability. A bit line selection circuit (100) of a flash memory includes transistors (BLSeO, BLSeE, BLSoO, BLSoE) in the column direction of bit lines (BL0-BL3), selecting a bit line pair composed of an even-numbered bit line (BL0) and an odd-numbered bit line (BL3) is selected by the transistors, in which a bit line pair (BL1, BL2) adjacent to the selected bit line pair is set as a non-selected bit line pair, and the selected bit line pair (BL0, BL3) is connected to page buffer/sensing circuit through an output node (BLS0, BLS1).

Abstract: According to one embodiment, a semiconductor memory includes: a first bit line; a first select transistor having a first terminal connected to the first bit line; a first memory cell connected to a second terminal of the first select transistor; a circuit connected to the first bit line and applying an erase voltage to be applied to the first memory cell to the bit line via the first terminal and the second terminal; and a diode connected to the first bit line and the first circuit.

Abstract: According to one embodiment, a semiconductor memory includes: a first bit line; a first select transistor having a first terminal connected to the first bit line; a first memory cell connected to a second terminal of the first select transistor; a circuit connected to the first bit line and applying an erase voltage to be applied to the first memory cell to the bit line via the first terminal and the second terminal; and a diode connected to the first bit line and the first circuit.

Abstract: According to one embodiment, a semiconductor memory includes: a first bit line; a first select transistor having a first terminal connected to the first bit line; a first memory cell connected to a second terminal of the first select transistor; a circuit connected to the first bit line and applying an erase voltage to be applied to the first memory cell to the bit line via the first terminal and the second terminal; and a diode connected to the first bit line and the first circuit.

Abstract: A semiconductor memory device according to an embodiment includes a memory chip and a circuit chip. The memory chip includes first and second joint metals. The circuit chip includes first and second sense amplifiers, and third and fourth joint metals facing the first and second joint metals, respectively. The first sense amplifier includes first and second active regions. The first active region includes a first transistor coupled between the third joint metal and the second active region. The second amplifier includes third and fourth active region. The third active region includes a second transistor coupled between the fourth joint metal and the fourth active region. The third and fourth joint metals overlap the first and third active regions, respectively.

Abstract: A semiconductor memory device includes a memory cell array layer which includes a first wiring line, a memory cell stacked on the first wiring line, and a second wiring line formed on the memory cell so as to intersect the first wiring line, wherein a step is formed in the first wiring line so that the height of an upper surface of the first wiring line in the memory cell array region where the memory cell array is formed is higher than the height in a peripheral region around the memory cell array region.

Abstract: A semiconductor memory device includes a memory cell array layer which includes a first wiring line, a memory cell stacked on the first wiring line, and a second wiring line formed on the memory cell so as to intersect the first wiring line, wherein a step is formed in the first wiring line so that the height of an upper surface of the first wiring line in the memory cell array region where the memory cell array is formed is higher than the height in a peripheral region around the memory cell array region.

Abstract: A semiconductor memory device includes a memory cell array layer which includes a first wiring line, a memory cell stacked on the first wiring line, and a second wiring line formed on the memory cell so as to intersect the first wiring line, wherein a step is formed in the first wiring line so that the height of an upper surface of the first wiring line in the memory cell array region where the memory cell array is formed is higher than the height in a peripheral region around the memory cell array region.

Abstract: A semiconductor memory device includes a memory cell array layer which includes a first wiring line, a memory cell stacked on the first wiring line, and a second wiring line formed on the memory cell so as to intersect the first wiring line, wherein a step is formed in the first wiring line so that the height of an upper surface of the first wiring line in the memory cell array region where the memory cell array is formed is higher than the height in a peripheral region around the memory cell array region.