Patents by Inventor Naohumi Ohashi

Naohumi Ohashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110291280
    Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.
    Type: Application
    Filed: August 10, 2011
    Publication date: December 1, 2011
    Inventors: Kazutoshi OHMORI, Tsuyoshi TAMARU, Naohumi OHASHI, Kiyohiko SATO, Hiroyuki MARUYAMA
  • Patent number: 8012871
    Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: September 6, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Kazutoshi Ohmori, Tsuyoshi Tamaru, Naohumi Ohashi, Kiyohiko Sato, Hiroyuki Maruyama
  • Publication number: 20100210107
    Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.
    Type: Application
    Filed: April 30, 2010
    Publication date: August 19, 2010
    Inventors: Kazutoshi Ohmori, Tsuyoshi Tamaru, Naohumi Ohashi, Kiyohiko Sato, Hiroyuki Maruyama
  • Patent number: 7723849
    Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: May 25, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Kazutoshi Ohmori, Tsuyoshi Tamaru, Naohumi Ohashi, Kiyohiko Sato, Hiroyuki Maruyama
  • Patent number: 7642652
    Abstract: A barrier layer and a copper film are successively formed on a silicon oxide film including a groove for wiring in the silicon oxide film and a silicon nitride film, both formed on a semiconductor substrate. Thereafter, the barrier layer and the copper film are removed from outside of the groove for wiring, thereby forming a wiring. Tungsten is selectively or preferentially grown on the wiring to selectively form a tungsten film on the wiring. After the formation of the copper film, a treatment with hydrogen may be performed. After the formation of the wiring, the semiconductor substrate may be cleaned with a cleaning solution capable of removing a foreign matter or a contaminant metal. After the formation of the wiring, a treatment with hydrogen is carried out.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: January 5, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Tatsuyuki Saito, Naohumi Ohashi, Toshinori Imai, Junji Noguchi, Tsuyoshi Tamaru
  • Publication number: 20080157219
    Abstract: In the manufacture of a semiconductor device having a high-performance and high-reliability, a silicon nitride film 17 for self alignment, which film is formed to cover the gate electrode of a MISFET, is formed at a substrate temperature of 400° C. or greater by plasma CVD using a raw material gas including monosilane and nitrogen. A silicon nitride film 44 constituting a passivation film is formed at a substrate temperature of about 350° C. by plasma CVD using a raw material gas including monosilane, ammonia and nitrogen. The hydrogen content contained in the silicon nitride film 17 is smaller than that contained in the silicon nitride film 44, making it possible to suppress hydrogen release from the silicon nitride film 17.
    Type: Application
    Filed: March 12, 2008
    Publication date: July 3, 2008
    Inventors: Tsuyoshi FUJIWARA, Masahiro Ushiyama, Katsuhiko Ichinose, Naohumi Ohashi, Tetsuo Saito
  • Publication number: 20080132059
    Abstract: Cu interconnections embedded in an interconnection slot of a silicon oxide film are formed by polishing using CMP to improve the insulation breakdown resistance of a copper interconnection formed using the Damascene method, and after a post-CMP cleaning step, the surface of the silicon oxide film and Cu interconnections is treated by a reducing plasma (ammonia plasma). Subsequently, a continuous cap film (silicon nitride film) is formed without vacuum break.
    Type: Application
    Filed: April 27, 2007
    Publication date: June 5, 2008
    Inventors: Junji Noguchi, Naohumi Ohashi, Tatsuyuki Saito
  • Publication number: 20080042282
    Abstract: A barrier layer and a copper film are successively formed on a silicon oxide film including a groove for wiring in the silicon oxide film and a silicon nitride film, both formed on a semiconductor substrate. Thereafter, the barrier layer and the copper film are removed from outside of the groove for wiring, thereby forming a wiring. Tungsten is selectively or preferentially grown on the wiring to selectively form a tungsten film on the wiring. After the formation of the copper film, a treatment with hydrogen may be performed. After the formation of the wiring, the semiconductor substrate may be cleaned with a cleaning solution capable of removing a foreign matter or a contaminant metal. After the formation of the wiring, a treatment with hydrogen is carried out.
    Type: Application
    Filed: October 15, 2007
    Publication date: February 21, 2008
    Inventors: Tatsuyuki SAITO, Naohumi Ohashi, Toshinori Imai, Junji Noguchi, Tsuyoshi Tamaru
  • Patent number: 7321171
    Abstract: A barrier layer and a copper film are successively formed on a silicon oxide film including a groove for wiring in the silicon oxide film and a silicon nitride film, both formed on a semiconductor substrate. Thereafter, the barrier layer and the copper film are removed from outside of the groove for wiring, thereby forming a wiring. Tungsten is selectively or preferentially grown on the wiring to selectively form a tungsten film on the wiring. After the formation of the copper film, a treatment with hydrogen may be performed. After the formation of the wiring, the semiconductor substrate may be cleaned with a cleaning solution capable of removing a foreign matter or a contaminant metal. After the formation of the wiring, a treatment with hydrogen is carried out.
    Type: Grant
    Filed: October 22, 2004
    Date of Patent: January 22, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Tatsuyuki Saito, Naohumi Ohashi, Toshinori Imai, Junji Noguchi, Tsuyoshi Tamaru
  • Patent number: 7232757
    Abstract: Cu interconnections embedded in an interconnection slot of a silicon oxide film are formed by polishing using CMP to improve the insulation breakdown resistance of a copper interconnection formed using the Damascene method, and after a post-CMP cleaning step, the surface of the silicon oxide film and Cu interconnections is treated by a reducing plasma (ammonia plasma). Subsequently, a continuous cap film (silicon nitride film) is formed without vacuum break.
    Type: Grant
    Filed: March 30, 2004
    Date of Patent: June 19, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Junji Noguchi, Naohumi Ohashi, Tatsuyuki Saito
  • Publication number: 20070105369
    Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.
    Type: Application
    Filed: December 28, 2006
    Publication date: May 10, 2007
    Inventors: Kazutoshi Ohmori, Tsuyoshi Tamaru, Naohumi Ohashi, Kiyohiko Sato, Hiroyuki Maruyama
  • Patent number: 7176121
    Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.
    Type: Grant
    Filed: October 15, 2003
    Date of Patent: February 13, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Kazutoshi Ohmori, Tsuyoshi Tamaru, Naohumi Ohashi, Kiyohiko Sato, Hiroyuki Maruyama
  • Publication number: 20070018327
    Abstract: In the manufacture of a semiconductor device having a high-performance and high-reliability, a silicon nitride film 17 for self alignment, which film is formed to cover the gate electrode of a MISFET, is formed at a substrate temperature of 400° C. or greater by plasma CVD using a raw material gas including monosilane and nitrogen. A silicon nitride film 44 constituting a passivation film is formed at a substrate temperature of about 350° C. by plasma CVD using a raw material gas including monosilane, ammonia and nitrogen. The hydrogen content contained in the silicon nitride film 17 is smaller than that contained in the silicon nitride film 44, making it possible to suppress hydrogen release from the silicon nitride film 17.
    Type: Application
    Filed: September 29, 2006
    Publication date: January 25, 2007
    Inventors: Tsuyoshi Fujiwara, Masahiro Ushiyama, Katsuhiko Ichinose, Naohumi Ohashi, Tetsuo Saito
  • Patent number: 7163886
    Abstract: In the manufacture of a semiconductor device having a high-performance and high-reliability, a silicon nitride film 17 for self alignment, which film is formed to cover the gate electrode of a MISFET, is formed at a substrate temperature of 400° C. or greater by plasma CVD using a raw material gas including monosilane and nitrogen. A silicon nitride film 44 constituting a passivation film is formed at a substrate temperature of about 350° C. by plasma CVD using a raw material gas including monosilane, ammonia and nitrogen. The hydrogen content contained in the silicon nitride film 17 is smaller than that contained in the silicon nitride film 44, making it possible to suppress hydrogen release from the silicon nitride film 17.
    Type: Grant
    Filed: August 13, 2004
    Date of Patent: January 16, 2007
    Assignees: Hitachi Tokyo Electronics Co., Ltd., Renesas Technology Corp.
    Inventors: Tsuyoshi Fujiwara, Masahiro Ushiyama, Katsuhiko Ichinose, Naohumi Ohashi, Tetsuo Saito
  • Patent number: 7084063
    Abstract: The copper interconnect formed by the use of a damascene technique is improved in dielectric breakdown strength (reliability). During post-CMP cleaning, alkali cleaning, a deoxidizing process due to hydrogen annealing or the like, and acid cleaning are carried out in this order. After the post-CMP cleaning and before forming an insulation film for a cap film, hydrogen plasma and ammonia plasma processes are carried out on the semiconductor substrate. In this way, a copper-based buried interconnect is formed in an interlayer insulation film structured of an insulation material having a low dielectric constant.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: August 1, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Junji Noguchi, Shoji Asaka, Nobuhiro Konishi, Naohumi Ohashi, Hiroyuki Maruyama
  • Publication number: 20050095844
    Abstract: A barrier layer and a copper film are successively formed on a silicon oxide film including a groove for wiring in the silicon oxide film and a silicon nitride film, both formed on a semiconductor substrate. Thereafter, the barrier layer and the copper film are removed from outside of the groove for wiring, thereby forming a wiring. Tungsten is selectively or preferentially grown on the wiring to selectively form a tungsten film on the wiring. After the formation of the copper film, a treatment with hydrogen may be performed. After the formation of the wiring, the semiconductor substrate may be cleaned with a cleaning solution capable of removing a foreign matter or a contaminant metal. After the formation of the wiring, a treatment with hydrogen is carried out.
    Type: Application
    Filed: October 22, 2004
    Publication date: May 5, 2005
    Inventors: Tatsuyuki Saito, Naohumi Ohashi, Toshinori Imai, Junji Noguchi, Tsuyoshi Tamaru
  • Publication number: 20050020021
    Abstract: In the manufacture of a semiconductor device having a high-performance and high-reliability, a silicon nitride film 17 for self alignment, which film is formed to cover the gate electrode of a MISFET, is formed at a substrate temperature of 400° C. or greater by plasma CVD using a raw material gas including monosilane and nitrogen. A silicon nitride film 44 constituting a passivation film is formed at a substrate temperature of about 350° C. by plasma CVD using a raw material gas including monosilane, ammonia and nitrogen. The hydrogen content contained in the silicon nitride film 17 is smaller than that contained in the silicon nitride film 44, making it possible to suppress hydrogen release from the silicon nitride film 17.
    Type: Application
    Filed: August 13, 2004
    Publication date: January 27, 2005
    Inventors: Tsuyoshi Fujiwara, Masahiro Ushiyama, Katsuhiko Ichinose, Naohumi Ohashi, Tetsuo Saito
  • Patent number: 6818546
    Abstract: A barrier layer and a copper film are successively formed on a silicon oxide film including a groove for wiring in the silicon oxide film and a silicon nitride film, both formed on a semiconductor substrate. Thereafter, the barrier layer and the copper film are removed from outside of the groove for wiring, thereby forming a wiring. Tungsten is selectively or preferentially grown on the wiring to selectively form a tungsten film on the wiring. After the formation of the copper film, a treatment with hydrogen may be performed. After the formation of the wiring, the semiconductor substrate may be cleaned with a cleaning solution capable of removing a foreign matter or a contaminant metal. After the formation of the wiring, a treatment with hydrogen is carried out.
    Type: Grant
    Filed: May 8, 2001
    Date of Patent: November 16, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Tatsuyuki Saito, Naohumi Ohashi, Toshinori Imai, Junji Noguchi, Tsuyoshi Tamaru
  • Publication number: 20040192032
    Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.
    Type: Application
    Filed: October 15, 2003
    Publication date: September 30, 2004
    Applicant: Renesas Technology Corp.
    Inventors: Kazutoshi Ohmori, Tsuyoshi Tamaru, Naohumi Ohashi, Kiyohiko Sato, Hiroyuki Maruyama
  • Publication number: 20040180536
    Abstract: At the end of a film-forming process of an insulator made of a silicon nitride film by a plasma CVD, introduction of the silane system gas is stopped, and thereafter a plasma discharge is performed for a predetermined time while introduction of the nitrogen-containing gas is continued, and then the plasma discharge is stopped. In this manner, it is possible to nitride an unreacted product on the silicon nitride film and to prevent drawbacks due to the unreacted product.
    Type: Application
    Filed: December 12, 2003
    Publication date: September 16, 2004
    Inventors: Tsuyoshi Fujiwara, Hiroyuki Maruyama, Naohumi Ohashi, Ken Tsugane