Patents by Inventor Naoichi Kawaguchi

Naoichi Kawaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7688109
    Abstract: The object of the present invention is to appropriately constitute such a semiconductor integrated circuit that mounts a plurality of semiconductor chips thereon so as to increase storage capacity. A semiconductor chip, including: a chip enable buffer circuit which outputs a chip enable signal in response to an output command of the chip enable signal; a standard chip enable pad which receives the output command; a first extension pad which supplies a first extension chip enable signal to the chip enable buffer circuit; a second extension pad which supplies a second extension chip enable signal to the chip enable buffer circuit; a first option pad which receives a first option signal; and a second option pad which receives a second option signal, is constituted.
    Type: Grant
    Filed: June 11, 2008
    Date of Patent: March 30, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Junji Monden, Naoichi Kawaguchi
  • Publication number: 20080309372
    Abstract: The object of the present invention is to appropriately constitute such a semiconductor integrated circuit that mounts a plurality of semiconductor chips thereon so as to increase storage capacity. A semiconductor chip, including: a chip enable buffer circuit which outputs a chip enable signal in response to an output command of the chip enable signal; a standard chip enable pad which receives the output command; a first extension pad which supplies a first extension chip enable signal (/CEm+1) to the chip enable buffer circuit; a second extension pad which supplies a second extension chip enable signal (CEm+1) to the chip enable buffer circuit; a first option pad which receives a first option signal; and a second option pad which receives a second option signal, is constituted.
    Type: Application
    Filed: June 11, 2008
    Publication date: December 18, 2008
    Inventors: Junji Monden, Naoichi Kawaguchi
  • Patent number: 6937515
    Abstract: A semiconductor memory device has a reduced number of sense amplifiers to suppress an increase in chip size and power consumption as integration is increased. A semiconductor memory device can be adapted to read out from a memory cell array in pages or bursts can include sense amplifiers (2) for reading out data for a page length or burst length in two parts, including a first half and second half, and a page buffer (3) for storing data for the page length or burst length read out from a memory cell array (1) by the sense amplifier (2).
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: August 30, 2005
    Assignee: NEC Electronics Corporation
    Inventors: Naoaki Sudo, Hiroshi Sugawara, Naoichi Kawaguchi
  • Publication number: 20040052124
    Abstract: A semiconductor memory device has a reduced number of sense amplifiers to suppress an increase in chip size and power consumption as integration is increased. A semiconductor memory device can be adapted to read out from a memory cell array in pages or bursts can include sense amplifiers (2) for reading out data for a page length or burst length in two parts, including a first half and second half, and a page buffer (3) for storing data for the page length or burst length read out from a memory cell array (1) by the sense amplifier (2).
    Type: Application
    Filed: August 29, 2003
    Publication date: March 18, 2004
    Inventors: Naoaki Sudo, Hiroshi Sugawara, Naoichi Kawaguchi