Abstract: A program preparation apparatus that can reduce power consumption and that can suppress malfunctions and the occurrence of noise by improving software is provided. An assembler prepares a relative object program based on an assembly source program. Next, the assembler changes the order of instructions included in the assembly source program in a range that does not influence the operational results in a CPU and, thereby, prepares another assembly source program so as to prepare a relative object program based on this assembly source program. Next, the assembler finds the respective maximum Hamming distance values between respective instructions for a plurality of relative object programs so that the program of which the maximum Hamming distance value is the lowest is determined as a formal relative object program.

Abstract: An external area judging unit judges according to an address signal of a CPU whether the access to an external memory or the access to a peripheral unit is desired. In cases where the access to the external memory (or the peripheral unit) is desired, a bus selection signal indicating the external memory (or the peripheral unit) is sent to a bus control unit, and a plurality of bus control signals received in the bus control unit from the CPU are sent to the external memory (or the peripheral unit) as a plurality of external bus signals based on a bus timing for the external memory (or the peripheral unit) to make the CPU gain access to the external memory (or the peripheral unit).

Abstract: A program preparation apparatus which can reduce power consumption and which can suppress malfunctions and the occurrence of noise by improving software is provided.

Abstract: An external area judging unit judges according to an address signal of a CPU whether the access to an external memory or the access to a peripheral unit is desired. In cases where the access to the external memory (or the peripheral unit) is desired, a bus selection signal indicating the external memory (or the peripheral unit) is sent to a bus control unit, and a plurality of bus control signals received in the bus control unit from the CPU are sent to the external memory (or the peripheral unit) as a plurality of external bus signals based on a bus timing for the external memory (or the peripheral unit) to make the CPU gain access to the external memory (or the peripheral unit).

Abstract: A serial I/O incorporated semiconductor device comprises a transmitting unit 4 including a transmission channel selection register 14 for selecting a transmitting pin to output transmit data and a receiving unit 5 including a receiving channel detection circuit 26 for detecting receiving pins that have received data; a receiving channel flag 27 set to have a predetermined value by the receiving channel detection circuit; a plural channels reception detection circuit 28 for detecting that received data is entered to a plurality of receiving pins; and a plural channels receiving flag 29 set to have a predetermined value by the plural channels reception detection circuit 28 detecting received data has been entered to the plurality of receiving pins; wherein when any one of the flags 23, 25, and 29 is set to a predetermined value, the receiving unit supplies the value to a CPU as a reception interrupt signal.

Abstract: A direct memory access controller has a data assembly function by means of a single temporary register. This single register used for a number of channels replaces temporary registers which have been necessary for the respective channels to carry out channel transition during data assembly. By controlling channel transition during data assembly, it is possible to carry out DMA transfers in which channel transition is made during data assembly, thereby preventing an increase in the chip size.