Patents by Inventor Naokatsu Suwanai
Naokatsu Suwanai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7705462Abstract: A semiconductor IC device which includes a circuit region and a peripheral region on a main surface of a semiconductor substrate, a first insulating film formed over the main surface, external terminals arranged in the peripheral region and formed over the first insulating film, a conductive guard ring formed over the first insulating film and provided around the external terminals, and second insulating films formed in the internal region and the peripheral region, the second insulating film in the peripheral region is formed over the first insulating film and over the guard ring and is contacting the external terminals, the second insulating films of the circuit region and that of the peripheral region are separately formed and are isolated from each other. Separate second insulating film may be formed over the wirings of one or more of existing wiring levels of the semiconductor device.Type: GrantFiled: September 21, 2009Date of Patent: April 27, 2010Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Ken Uchikoshi, Naokatsu Suwanai, Atsushi Tachigami, Katsuhiko Hotta, Masashi Sahara, Kazuhiko Sato
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Publication number: 20100007024Abstract: A semiconductor IC device which includes a circuit region and a peripheral region on a main surface of a semiconductor substrate, a first insulating film formed over the main surface, external terminals arranged in the peripheral region and formed over the first insulating film, a conductive guard ring formed over the first insulating film and provided around the external terminals, and second insulating films formed in the internal region and the peripheral region, the second insulating film in the peripheral region is formed over the first insulating film and over the guard ring and is contacting the external terminals, the second insulating films of the circuit region and that of the peripheral region are separately formed and are isolated from each other. Separate second insulating film may be formed over the wirings of one or more of existing wiring levels of the semiconductor device.Type: ApplicationFiled: September 21, 2009Publication date: January 14, 2010Inventors: Ken UCHIKOSHI, Naokatsu Suwanai, Atsushi Tachigami, Katsuhiko Hotta, Masahi Sahara, Kazuhiko Sato
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Patent number: 7615848Abstract: A semiconductor IC device which includes a circuit region and a peripheral region on a main surface of a semiconductor substrate, a first insulating film formed over the main surface, external terminals arranged in the peripheral region and formed over the first insulating film, a conductive guard ring formed over the first insulating film and provided around the external terminals, and second insulating films formed in the internal region and the peripheral region, the second insulating film in the peripheral region is formed over the first insulating film and over the guard ring and is contacting the external terminals, the second insulating films of the circuit region and that of the peripheral region are separately formed and are isolated from each other. Separate second insulating film may be formed over the wirings of one or more of existing wiring levels of the semiconductor device.Type: GrantFiled: June 12, 2008Date of Patent: November 10, 2009Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Ken Uchikoshi, Naokatsu Suwanai, Atsushi Tachigami, Katsuhiko Hotta, Masashi Sahara, Kazuhiko Sato
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Publication number: 20080277794Abstract: A semiconductor IC device which includes a circuit region and a peripheral region on a main surface of a semiconductor substrate, a first insulating film formed over the main surface, external terminals arranged in the peripheral region and formed over the first insulating film, a conductive guard ring formed over the first insulating film and provided around the external terminals, and second insulating films formed in the internal region and the peripheral region, the second insulating film in the peripheral region is formed over the first insulating film and over the guard ring and is contacting the external terminals, the second insulating films of the circuit region and that of the peripheral region are separately formed and are isolated from each other. Separate second insulating film may be formed over the wirings of one or more of existing wiring levels of the semiconductor device.Type: ApplicationFiled: June 12, 2008Publication date: November 13, 2008Inventors: Ken Uchikoshi, Naokatsu Suwanai, Atsushi Tachigami, Katsuhiko Hotta, Masashi Sahara, Kazuhiko Sato
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Patent number: 7400046Abstract: A semiconductor IC device which includes a circuit region and a peripheral region on a main surface of a semiconductor substrate, a first insulating film formed over the main surface, external terminals arranged in the peripheral region and formed over the first insulating film, a conductive guard ring formed over the first insulating film and provided around the external terminals, and second insulating films formed in the internal region and the peripheral region, the second insulating film in the peripheral region is formed over the first insulating film and over the guard ring and is contacting the external terminals, the second insulating films of the circuit region and that of the peripheral region are separately formed and are isolated from each other. Separate second insulating film may be formed over the wirings of one or more of existing wiring levels of the semiconductor device.Type: GrantFiled: May 31, 2007Date of Patent: July 15, 2008Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Ken Uchikoshi, Naokatsu Suwanai, Atsushi Tachigami, Katsuhiko Hotta, Masashi Sahara, Kazuhiko Sato
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Patent number: 7303986Abstract: An insulating portion of the respective wiring layers for a semiconductor device is constituted of insulating films. The one insulating film is made of a material whose conductivity is higher than that of the other insulating film that is made of an ordinary silicon oxide film and is provided in contact with the wiring. An electric charge accumulated in the wiring generated in the course of manufacture of the semiconductor device is discharged through the one insulating film at a stage where a charge accumulation in the wiring is low. This permits the heat release value generated through the discharge to be suppressed to a low level, and the short-circuiting-failure between adjacent wirings to be suppressed or prevented.Type: GrantFiled: November 21, 2006Date of Patent: December 4, 2007Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Ken Uchikoshi, Naokatsu Suwanai, Atsushi Tachigami, Katsuhiko Hotta, Masashi Sahara, Kazuhiko Sato
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Publication number: 20070228574Abstract: A semiconductor IC device which includes a circuit region and a peripheral region on a main surface of a semiconductor substrate, a first insulating film formed over the main surface, external terminals arranged in the peripheral region and formed over the first insulating film, a conductive guard ring formed over the first insulating film and provided around the external terminals, and second insulating films formed in the internal region and the peripheral region, the second insulating film in the peripheral region is formed over the first insulating film and over the guard ring and is contacting the external terminals, the second insulating films of the circuit region and that of the peripheral region are separately formed and are isolated from each other. Separate second insulating film may be formed over the wirings of one or more of existing wiring levels of the semiconductor device.Type: ApplicationFiled: May 31, 2007Publication date: October 4, 2007Inventors: Ken Uchikoshi, Naokatsu Suwanai, Atsushi Tachigami, Katsuhiko Hotta, Masashi Sahara, Kazuhiko Sato
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Publication number: 20070066050Abstract: An insulating portion of the respective wiring layers for a semiconductor device is constituted of insulating films. The one insulating film is made of a material whose conductivity is higher than that of the other insulating film that is made of an ordinary silicon oxide film and is provided in contact with the wiring. An electric charge accumulated in the wiring generated in the course of manufacture of the semiconductor device is discharged through the one insulating film at a stage where a charge accumulation in the wiring is low. This permits the heat release value generated through the discharge to be suppressed to a low level, and the short-circuiting-failure between adjacent wirings to be suppressed or prevented.Type: ApplicationFiled: November 21, 2006Publication date: March 22, 2007Inventors: Ken Uchikoshi, Naokatsu Suwanai, Atsushi Tachigami, Katsuhiko Hotta, Masashi Sahara, Kazuhiko Sato
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Patent number: 7189637Abstract: An insulating portion of the respective wiring layers for a semiconductor device is constituted of insulating films. The one insulating film is made of a material whose conductivity is higher than that of the other insulating film that is made of an ordinary silicon oxide film and is provided in contact with the wiring. An electric charge accumulated in the wiring generated in the course of manufacture of the semiconductor device is discharged through the one insulating film at a stage where a charge accumulation in the wiring is low. This permits the heat release value generated through the discharge can be suppressed to a low level, and the short-circuiting failure between adjacent wirings can be suppressed or prevented.Type: GrantFiled: December 11, 2003Date of Patent: March 13, 2007Assignees: Renesas Technology Corp., Hitachi Ulsi Systems Co., Ltd.Inventors: Ken Uchikoshi, Naokatsu Suwanai, Atsushi Tachigami, Katsuhiko Hotta, Masashi Sahara, Kazuhiko Sato
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Publication number: 20040121571Abstract: An insulating portion of the respective wiring layers for a semiconductor device is constituted of insulating films. The one insulating film is made of a material whose conductivity is higher than that of the other insulating film made of an ordinary silicon oxide film and is provided in contact with the wiring. An electric charge accumulated in the wiring generated in the course of the manufacture of the semiconductor device is discharged through the one insulating film at a stage where a charge accumulation in the wiring is low. This permits the heat release value generated through the discharge can be suppressed low, and the short-circuiting failure between adjacent wirings can be suppressed or prevented.Type: ApplicationFiled: December 11, 2003Publication date: June 24, 2004Inventors: Ken Uchikoshi, Naokatsu Suwanai, Atsushi Tachigami, Katsuhiko Hotta, Masashi Sahara, Kazuhiko Sato
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Publication number: 20020003305Abstract: A dummy interconnection is formed below a bonding pad formed on an interlayer insulating film composed of a silicon oxide film, an SOG film, and a silicon oxide film. The adhesion of layers is improved by increasing a direct contact area between these silicon oxide films formed of the same material.Type: ApplicationFiled: August 23, 2001Publication date: January 10, 2002Inventors: Masashi Umakoshi, Naokatsu Suwanai, Atsushi Ogishima
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Semiconductor memory circuit device and method for fabricating a semiconductor memory device circuit
Patent number: 6043118Abstract: In a semiconductor memory circuit device wherein each memory cell is constituted by a series circuit of a memory cell selecting MISFET and an information storing capacitor of a stacked structure, there are present in a first region as a memory cell array region a first MISFET having a gate electrode and source and drain regions; first and second capacity electrodes and a dielectric film extending onto a first insulating film on the gate electrode; a second insulating film positioned on the second capacity electrode; and a first wiring positioned on the second insulating film, while in a second region as a peripheral circuit region there are present a second MISFET having a gate electrode and source and drain regions; a first insulating film on the gate electrode; a third insulating film on the first insulating film; a second insulating film on the third insulating film; and a second wiring on the second insulating film.Type: GrantFiled: February 13, 1997Date of Patent: March 28, 2000Assignee: Hitachi, Ltd.Inventors: Naokatsu Suwanai, Hiroyuki Miyazawa, Atushi Ogishima, Masaki Nagao, Kyoichiro Asayama, Hiroyuki Uchiyama, Yoshiyuki Kaneko, Takashi Yoneoka, Kozo Watanabe, Kazuya Endo, Hiroki Soeda -
Patent number: 5994762Abstract: A semiconductor integrated circuit device is provided in which an interlayer insulation film deposited on a semiconductor chip includes a boron-containing silicon oxide film and a second film deposited on the boron-containing silicon oxide film. A guard ring is disposed adjacent to the periphery of the semiconductor chip, and a slit is disposed between the guard ring and the periphery of the chip. The depth of the slit is selected such that cracks formed on the boundary between the BPSG film and the second film are inhibited by the slit from intruding further along the boundary to the inside of the chip, thereby preventing moisture or obstacles from reaching the inside of the chip through the cracks.Type: GrantFiled: July 26, 1996Date of Patent: November 30, 1999Assignee: Hitachi, Ltd.Inventors: Naokatsu Suwanai, Yasuhide Fujioka
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Patent number: 5631182Abstract: In a semiconductor memory circuit device wherein each memory cell is constituted by a series circuit of a memory cell selecting MISFET and an information storing capacitor of a stacked structure, there are present in a first region as a memory cell array region a first MISFET having a gate electrode and source and drain regions; first and second capacity electrodes and a dielectric film extending onto a first insulating film on the gate electrode; a second insulating film positioned on the second capacity electrode; and a first wiring positioned on the second insulating film, while in a second region as a peripheral circuit region there are present a second MISFET having a gate electrode and source and drain regions; a first insulating film on the gate electrode; a third insulating film on the first insulating film; a second insulating film on the third insulating film; and a second wiring on the second insulating film.Type: GrantFiled: October 18, 1994Date of Patent: May 20, 1997Assignee: Hitachi, Ltd.Inventors: Naokatsu Suwanai, Hiroyuki Miyazawa, Atushi Ogishima, Masaki Nagao, Kyoichiro Asayama, Hiroyuki Uchiyama, Yoshiyuki Kaneko, Takashi Yoneoka, Kozo Watanabe, Kazuya Endo, Hiroki Soeda
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Patent number: 5389558Abstract: In a semiconductor memory circuit device wherein each memory cell is constituted by a series circuit of a memory cell selecting MISFET and an information storing capacitor of a stacked structure, there are present in a first region as a memory cell array region a first MISFET having a gate electrode and source and drain regions; first and second capacity electrodes and a dielectric film extending onto a first insulating film on the gate electrode; a second insulating film positioned on the second capacity electrode; and a first wiring positioned on the second insulating film, while in a second region as a peripheral circuit region there are present a second MISFET having a gate electrode and source and drain regions; a first insulating film on the gate electrode; a third insulating film on the first insulating film; a second insulating film on the third insulating film; and a second wiring on the second insulating film.Type: GrantFiled: August 10, 1993Date of Patent: February 14, 1995Assignee: Hitachi, Ltd.Inventors: Naokatsu Suwanai, Hiroyuki Miyazawa, Atushi Ogishima, Masaki Nagao, Kyoichiro Asayama, Hiroyuki Uchiyama, Yoshiyuki Kaneko, Takashi Yoneoka, Kozo Watanabe, Kazuya Endo, Hiroki Soeda
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Patent number: 5237187Abstract: In a semiconductor memory circuit device wherein each memory cell is constituted by a series circuit of a memory cell selecting MISFET and an information storing capacitor of a stacked structure, there are present in a first region, which is a memory cell array region, a first MISFET having a gate electrode and source and drain regions; first and second capacitor electrodes and a dielectric film extended over a first insulating film and over the gate electrode; a second insulating film disposed on the second capacitor electrode; a third insulating film interposed between the first insulating film and first capacitor electrode; and a first wiring positioned on the second insulating film.Type: GrantFiled: November 27, 1991Date of Patent: August 17, 1993Assignee: Hitachi, Ltd.Inventors: Naokatsu Suwanai, Hiroyuki Miyazawa, Atushi Ogishima, Masaki Nagao, Kyoichiro Asayama, Hiroyuki Uchiyama, Yoshiyuki Kaneko, Takashi Yoneoka, Kozo Watanabe, Kazuya Endo, Hiroki Soeda
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Patent number: 5025741Abstract: A semiconductor integrated circuit device having a wiring line of aluminum film or aluminum alloy film covered with a silicon insulation film and connected to the semiconductor region formed on the principal surface of a single crystal silicon substrate, with a polycrystalline silicon film interposed, wherein said silicon film is a polycrystalline silicon film composed of large crystal grains which is formed by depositing in amorphous state and then heat-treating the deposited film, said polycrystalline silicon film reduces the amount of silicon atoms which separates out in said wiring line. Also said wiring line is provided with a shielding film which is disposed between said insulation film and at least the upper surface and lower surface of said wiring line and which prevents silicon atoms from separating out from said insulation film.Type: GrantFiled: April 28, 1989Date of Patent: June 25, 1991Assignee: Hitachi, Ltd.Inventors: Naokatsu Suwanai, Osamu Tsuchiya