Abstract: A circuit embodying the invention includes a gating circuit responsive to a first control signal and to a second externally supplied control signal having an active state and an inactive state. The first control signal is produced by a power supply circuit which is responsive to the application of an externally supplied operating voltage for producing an "internal" operating voltage and which produces the first control signal having an active state when the internal operating voltage reaches a predetermined value. The gating circuit has an output for producing a third control signal which is enabling only if the second control signal goes from its inactive state to its active state when the first control signal is already in, and remains in, its active state. The gating circuit prevents a chip from operating in an unintended mode at power-up.

Abstract: A circuit embodying the invention includes a gating circuit responsive to a first control signal and to a second externally supplied control signal having an active state and an inactive state. The first control signal is produced by a power supply circuit which is responsive to the application of an externally supplied operating voltage for producing an "internal" operating voltage and which produces the first control signal having an active state when the internal operating voltage reaches a predetermined value. The gating circuit has an output for producing a third control signal which is enabling only if the second control signal goes from its inactive state to its active state when the first control signal is already in, and remains in, its active state. The gating circuit prevents a chip from operating in an unintended mode at power-up.

Abstract: A semiconductor integrated circuit includes a bias voltage regulation circuit having variable resistors which are provided between voltage output circuits of higher and lower potential sides and changes corresponding to a specified condition such as V.sub.CC and a temperature. The variable resistors and bias voltage output circuits form a V.sub.CC divider, and the variable resistors properly regulate a bias voltage supplied to an oscillation circuit corresponding to each of the specified conditions. Accordingly, if the oscillation circuit is used in an automatic refresh circuit of a PSRAM, an increase of a refresh operation frequency is suppressed regardless of an increase in V.sub.CC. Since a temperature depending variable resistor causes a resistance value to be reduced by the predetermined characteristics against the temperature increase, it is possible to set an oscillation frequency to provide a desired pause for guarantee of circuit operation.

Abstract: A semiconductor memory device has a plurality of memory cell arrays; input and output sections each provided so as to correspond to each of the memory cell arrays; and an allocating section provided between the memory cell arrays and the input and output sections, for allocating one of the memory cell arrays to one of the input output sections in ordinary mode, and a plurality of the memory cell arrays to one of the input and output sections in test mode. In the operation test mode, since only a part of the input and output sections are used, it is possible to decrease the number of chips connected to the I/O pins (whose maximum number is limited) of the tester so as to be testable simultaneously, so that the number of chips whose operation tests can be implemented simultaneously can be increased, thus reducing the time required for the operation test of the memory device as a whole.

Abstract: A semiconductor memory device is adapted for storing, as a unit of memory information, multiple-bit data constituted by signal data comprised of bit data of 2.sup.n bits (n is a natural number) and remainder data comprised of bit data of C bits (C is a natural number, C<2.sup.n). This semiconductor memory device includes a plurality of circuit blocks comprising, e.g., two memory cell groups each comprised of a plurality of memory cells, and a row decoder and a column decoder adapted for allowing respective desired ones of the memory cells within the memory cell groups to be selectively active. Thus, the row decoder and the column decoder become operative so that the bit data serving as the signal data is assigned to one or plural circuit blocks by one bit or plural bits, and the bit data serving as the remainder data is assigned to any circuit block in which bit assignment has been made.

Abstract: A control circuit for controlling an operation mode in a pseudo-static RAM. A chip enable control circuit generates a first group of control signals in synchronism with a change in level of a chip enable signal. A second control circuit receives a chip select signal and the first group of control signals, latches a chip select signal on the basis of a signal of the first group of control signals, and generates a second control signal in accordance with the latched signal. A third control circuit controls a write enable signal with an inverted replica of the second control signal and an inverted replica of a predetermined one of the first control signals in the first group of control signals.

Abstract: The semiconductor memory device comprises first and second terminals connected to first and second power sources, respectively; a detection circuit for outputting a detection signal when the second power source voltage becomes higher by a predetermined value than the first power source voltage; a power source switching circuit for controlling the memory device so that power is supplied from the second power source, in response to the detection signal; and a data hold control circuit for controlling the memory device so that data are kept stored therein in response to the detection signal. Since these circuits are incorporated inside the chip, the packaging efficiency or density of the memory devices can be improved when the memory devices are integrated on a semiconductor substrate.

Abstract: The semiconductor circuit device comprises a substrate bias generating circuit, a substrate voltage detecting circuit, and a substrate impedance adjusting circuit. When the detected substrate voltage decreases below a predetermined level, the substrate impedance adjusting circuit forms a through route between a substrate voltage terminal and any given terminal higher in potential than the substrate voltage terminal, to increase the substrate voltage at high speed, thus stabilizing threshold voltages or operation limit voltages of device elements which are subjected to the influence of the substrate voltage. Further, when the substrate voltage returns to the predetermined level, the substrate impedance adjusting circuit cuts off the formed through route for reduction of power consumption.

Abstract: A substrate bias voltage generator circuit has a substrate bias voltage detector circuit, a substrate bias driver circuit, and a charge pump circuit. the substrate bias voltage detector circuit detects a substrate bias voltage applied to a semiconductor substrate and outputs a substrate bias voltage detection signal. The substrate bias detector circuit includes a P-channel transistor with a gate terminal and an N-channel transistor with a substrate terminal, both terminals being connected to the semiconductor substrate and the substrate bias voltage which is a back bias for the N-channel transistor.

Abstract: A first chip enable signal for determining the operation timing of a memory chip is supplied to a first chip enable input circuit. A second chip enable signal for selectively specifying the stand-by mode/operative mode of the memory chip and an output signal of the first chip enable input circuit are supplied to a second chip enable input circuit. The second chip enable signal is received and latched by means of the second chip enable input circuit when the first chip enable signal is set active. An internal chip enable signal is output from the second chip enable input circuit based on the latched output to set the internal circuit of the memory chip into the stand-by mode.

Abstract: In the buffer circuit for an integrated circuit according to this invention a load MOS transistor and a drive MOS transistor are connected in series between a power source potential node and a ground potential node of the integrated circuit. A constant current circuit means connected in series with a circuit including the load MOS transistor and the drive MOS transistor.

Abstract: A dynamic type semiconductor memory device having refreshing function includes a clock pulse generating circuit having a row clock pulse generating section which includes a plurality of cascade-connected delay circuits, a plurality of MOS transistors selectively connected between said delay circuits, and a gate control circuit for changing conduction resistances of the MOS transistors according to the level of a refreshing signal.