Abstract: An all digital PLL-based data detector for use in a disc media reproducer or recorder for receiving input read data read from a disc storage medium and providing an output sync signal and synchronized read data with jitter substantially eliminated. The PLL circuit is provided with a circuit for limiting the fed-back count value to a predetermined range so as to limit the internal sync signal to a desired range, a circuit for resetting a predetermined portion of the digital PLL-based circuit during an invalid period when input read data are expected to be invalid to thereby ensuring a normal operation after the invalid period, and/or a circuit for generating, from a given clock signal of a first frequency, a second clock signal of a second frequency different from the first frequency to thereby support a different data rate.

Abstract: A method for copying data in disk recording media, and disk recording apparatus. At copying data recorded in a disk to another disk, occurrence of seek at the copy source is eliminated or suppressed below a specified value during reading data to reduce read time. At the target disk, data is rearranged according to video scenes or files, or file control information is rewritten to maintain the data structure of the copy source.

Abstract: A method for copying data in disk recording media, and disk recording apparatus. At copying data recorded in a disk to another disk, occurrence of seek at the copy source is eliminated or suppressed below a specified value during reading data to reduce read time. At the target disk, data is rearranged according to video scenes or files, or file control information is rewritten to maintain the data structure of the copy source.

Abstract: An all digital PLL-based data detector for use in a disc media reproducer or recorder for receiving input read data read from a disc storage medium and providing an output sync signal and synchronized read data with jitter substantially eliminated. The PLL circuit is provided with a circuit for limiting the fed-back count value to a predetermined range so as to limit the internal sync signal to a desired range, a circuit for resetting a predetermined portion of the digital PLL-based circuit during an invalid period when input read data are expected to be invalid to thereby ensuring a normal operation after the invalid period, and/or a circuit for generating, from a given clock signal of a first frequency, a second clock signal of a second frequency different from the first frequency to thereby support a different data rate.