Patents by Inventor Naoki Handa

Naoki Handa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor integrated circuit device having internal circuit with plural power supply regions
    Patent number: 8214670
    Abstract: A semiconductor integrated circuit has an internal circuit to which operation power is supplied or interrupted, and a power supply control circuit for controlling the supply and interruption of operation power to the internal circuit in accordance with an operation mode. The power supply control circuit has a storage circuit and a power supply control sequence circuit. The storage circuit inputs and holds switching instruction data for instructing switching between supply and interruption of the operation power and low-power-consumption-mode data determining an operation mode of the interruption of operation power and cancellation of the interruption.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: July 3, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Hiromichi Ishikura, Toyohiro Shimogawa, Katsumasa Uchiyama, Shoichiro Chiba, Naoki Handa
  • SEMICONDUCTOR INTEGRATED CIRCUIT
    Publication number: 20100275048
    Abstract: A semiconductor integrated circuit has an internal circuit to which operation power is supplied or interrupted, and a power supply control circuit for controlling the supply and interruption of operation power to the internal circuit in accordance with an operation mode. The power supply control circuit has a storage circuit and a power supply control sequence circuit. The storage circuit inputs and holds switching instruction data for instructing switching between supply and interruption of the operation power and low-power-consumption-mode data determining an operation mode of the interruption of operation power and cancellation of the interruption.
    Type: Application
    Filed: July 8, 2010
    Publication date: October 28, 2010
    Inventors: HIROMICHI ISHIKURA, Toyohiro Shimogawa, Katsumasa Uchiyama, Shoichiro Chiba, Naoki Handa
  • Semiconductor integrated circuit
    Patent number: 7765415
    Abstract: A semiconductor integrated circuit has an internal circuit to which operation power is supplied or interrupted, and a power supply control circuit for controlling the supply and interruption of operation power to the internal circuit in accordance with an operation mode. The power supply control circuit has a storage circuit and a power supply control sequence circuit. The storage circuit inputs and holds switching instruction data for instructing switching between supply and interruption of the operation power and low-power-consumption-mode data determining an operation mode of the interruption of operation power and cancellation of the interruption.
    Type: Grant
    Filed: July 18, 2007
    Date of Patent: July 27, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Hiromichi Ishikura, Toyohiro Shimogawa, Katsumasa Uchiyama, Shoichiro Chiba, Naoki Handa
  • Semiconductor integrated circuit
    Publication number: 20080034242
    Abstract: A semiconductor integrated circuit has an internal circuit to which operation power is supplied or interrupted, and a power supply control circuit for controlling the supply and interruption of operation power to the internal circuit in accordance with an operation mode. The power supply control circuit has a storage circuit and a power supply control sequence circuit. The storage circuit inputs and holds switching instruction data for instructing switching between supply and interruption of the operation power and low-power-consumption-mode data determining an operation mode of the interruption of operation power and cancellation of the interruption.
    Type: Application
    Filed: July 18, 2007
    Publication date: February 7, 2008
    Inventors: Hiromichi Ishikura, Toyohiro Shimogawa, Katsumasa Uchiyama, Shoichiro Chiba, Naoki Handa
  • Semiconductor memory device and method of testing short circuits between word lines and bit lines
    Patent number: 6781902
    Abstract: The present invention provides a semiconductor device and a testing method capable of easily detecting a short circuit in a memory circuit with high precision and efficiently detecting a short circuit in a memory circuit. A memory circuit in which memory cells are disposed at intersections of a plurality of word lines and a plurality of bit lines performs, in a test mode, an operation of applying a predetermined potential to neighboring ones of a plurality of word lines or bit lines, an operation of selecting a plurality of word lines and applying a ground potential of the circuit to all of the plurality of bit lines, and an operation of setting all of the plurality of bit lines at a predetermined potential corresponding to the selection level of the word lines and setting all of the plurality of word lines into a non-selection state.
    Type: Grant
    Filed: July 9, 2003
    Date of Patent: August 24, 2004
    Assignees: Renesas Technology Corp., Renesas Northern Japan Semiconductor, Inc., Hitachi Device Engineering Co., Ltd.
    Inventors: Atsuo Oumiya, Kouta Tanaka, Naoki Handa, Kenji Kobayashi
  • Semiconductor device and a method of testing thereof
    Publication number: 20040042279
    Abstract: The present invention provides a semiconductor device and a testing method capable of easily detecting a short circuit in a memory circuit with high precision and efficiently detecting a short circuit in a memory circuit. A memory circuit in which memory cells are disposed at intersections of a plurality of word lines and a plurality of bit lines performs, in a test mode, an operation of applying a predetermined potential to neighboring ones of a plurality of word lines or bit lines, an operation of selecting a plurality of word lines and applying a ground potential of the circuit to all of the plurality of bit lines, and an operation of setting all of the plurality of bit lines at a predetermined potential corresponding to the selection level of the word lines and setting all of the plurality of word lines into a non-selection state.
    Type: Application
    Filed: July 9, 2003
    Publication date: March 4, 2004
    Applicants: Hitachi, Ltd., Renesas Northern Japan Semiconductor, Inc., Hitachi Device Engineering Co., Ltd.
    Inventors: Atsuo Oumiya, Kouta Tanaka, Naoki Handa, Kenji Kobayashi