Patents by Inventor Naoki Idani
Naoki Idani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8991042Abstract: A method for fabricating a semiconductor device includes (a) depositing an insulating film on a semiconductor substrate; (b) forming a recess in the insulating film; (c) depositing a conductive film on the insulating film while filling the recess with the conductive film; and (d) polishing the conductive film. Step (d) includes a first polishing substep of using a first polisher pad conditioned with a first dresser and a second polishing substep of using a second polisher pad conditioned with a second dresser different from the first dresser.Type: GrantFiled: September 14, 2012Date of Patent: March 31, 2015Assignee: Fujitsu Semiconductor LimitedInventors: Manabu Sakamoto, Tetsuya Shirasu, Naoki Idani
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Patent number: 8658529Abstract: An oxide film is formed on an inner surface of a via hole in which a through electrode is to be formed, and thereafter a Cu film is embedded in the via hole. When an excess Cu film formed on a first interlayer insulating film is removed by a CMP method, the oxide film is also polished and reduced in thickness. Using the oxide film reduced in thickness as a hard mask, a wiring trench is formed in the first interlayer insulating film. At this time, the oxide film is further reduced in thickness. After a conductive material is embedded in the wiring trench, an excess conductive material is removed by polishing. At this time, the remaining oxide film is removed entirely by the polishing.Type: GrantFiled: April 25, 2012Date of Patent: February 25, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Naoki Idani
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Patent number: 8614146Abstract: A semiconductor device manufacture method includes: forming an insulating film above a semiconductor substrate; etching the insulating film to form a dummy groove having a first depth, a wiring groove having a second depth deeper than the first depth, and a via hole to be disposed on a bottom of the wiring groove; depositing a conductive material in the dummy groove, wiring groove and via hole and above the insulating film; and polishing and removing the conductive material above the insulating film.Type: GrantFiled: February 11, 2011Date of Patent: December 24, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Satoshi Takesako, Naoki Idani
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Patent number: 8496758Abstract: A front surface of the wafer is contacted with a straight-shaped front surface cleaning brush, and a pressure is applied on the front surface cleaning brush from both ends to enlarge the diameters in both end portions of the front surface cleaning brush. The front surface cleaning brush rotates with a shaft being an axis. An inner surface of the front surface cleaning brush is directly in contact with a surface of the shaft. The front surface cleaning brush is composed of a single structure made of synthetic resin.Type: GrantFiled: February 23, 2011Date of Patent: July 30, 2013Assignee: Fujitsu Semiconductor LimitedInventor: Naoki Idani
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Publication number: 20130012019Abstract: A method for fabricating a semiconductor device includes (a) depositing an insulating film on a semiconductor substrate; (b) forming a recess in the insulating film; (c) depositing a conductive film on the insulating film while filling the recess with the conductive film; and (d) polishing the conductive film. Step (d) includes a first polishing substep of using a first polisher pad conditioned with a first dresser and a second polishing substep of using a second polisher pad conditioned with a second dresser different from the first dresser.Type: ApplicationFiled: September 14, 2012Publication date: January 10, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Manabu SAKAMOTO, Tetsuya SHIRASU, Naoki IDANI
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Publication number: 20120276736Abstract: An oxide film is formed on an inner surface of a via hole in which a through electrode is to be formed, and thereafter a Cu film is embedded in the via hole. When an excess Cu film formed on a first interlayer insulating film is removed by a CMP method, the oxide film is also polished and reduced in thickness. Using the oxide film reduced in thickness as a hard mask, a wiring trench is formed in the first interlayer insulating film. At this time, the oxide film is further reduced in thickness. After a conductive material is embedded in the wiring trench, an excess conductive material is removed by polishing. At this time, the remaining oxide film is removed entirely by the polishing.Type: ApplicationFiled: April 25, 2012Publication date: November 1, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Naoki Idani
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Patent number: 8286344Abstract: A method for fabricating a semiconductor device includes (a) depositing an insulating film on a semiconductor substrate; (b) forming a recess in the insulating film; (c) depositing a conductive film on the insulating film while filling the recess with the conductive film; and (d) polishing the conductive film. Step (d) includes a first polishing substep of using a first polisher pad conditioned with a first dresser and a second polishing substep of using a second polisher pad conditioned with a second dresser different from the first dresser.Type: GrantFiled: August 28, 2008Date of Patent: October 16, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Manabu Sakamoto, Tetsuya Shirazu, Naoki Idani
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Publication number: 20120171931Abstract: A polishing method includes a first polishing step of halfway polishing a film to be polished formed on a substrate, and a second polishing step of further polishing the polished film, wherein a first film thickness profile showing an in-plane distribution of a film thickness of the polished film after the second polishing step for a first substrate is measured, and the first polishing step for a second substrate is executed to obtain a second film thickness profile which has a size relation in a film thickness opposite to the first film thickness profile.Type: ApplicationFiled: March 9, 2012Publication date: July 5, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Naoki Idani
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Patent number: 8153525Abstract: A polishing method includes a first polishing step of halfway polishing a film to be polished formed on a substrate, and a second polishing step of further polishing the polished film, wherein a first film thickness profile showing an in-plane distribution of a film thickness of the polished film after the second polishing step for a first substrate is measured, and the first polishing step for a second substrate is executed to obtain a second film thickness profile which has a size relation in a film thickness opposite to the first film thickness profile.Type: GrantFiled: March 26, 2008Date of Patent: April 10, 2012Assignee: Fujitsu Semiconductor LimitedInventor: Naoki Idani
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Publication number: 20120001344Abstract: A semiconductor device manufacture method includes: forming an insulating film above a semiconductor substrate; etching the insulating film to form a dummy groove having a first depth, a wiring groove having a second depth deeper than the first depth, and a via hole to be disposed on a bottom of the wiring groove; depositing a conductive material in the dummy groove, wiring groove and via hole and above the insulating film; and polishing and removing the conductive material above the insulating film.Type: ApplicationFiled: February 11, 2011Publication date: January 5, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Satoshi TAKESAKO, Naoki IDANI
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Publication number: 20110138553Abstract: A wafer on which a CMP processing is completed is rotated. A front surface cleaning brush and a rear surface cleaning brush are made contact both surfaces of the wafer while being rotated. After the front surface cleaning brush and the rear surface cleaning brush are made to contact the wafer, both end portions of the front surface cleaning brush and the rear surface cleaning brush are deformed by means of pressurizing both ends of the front surface cleaning brush and the rear surface cleaning brush by pressure portions. That is, the both end portions of the front surface cleaning brush and the rear surface cleaning brush are compressed to enlarge diameters in the both end portions. As a consequence, the entire front surface of the wafer is made to contact the front surface cleaning brush substantially evenly, even if the wafer is warped into a shape of a mound. Therefore, a cleaning efficiency of the outer peripheral portion of the wafer improves.Type: ApplicationFiled: February 23, 2011Publication date: June 16, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Naoki IDANI
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Patent number: 7951715Abstract: The method comprises the step polishing the surface of a film-to-be-polished formed over a semiconductor substrate 10 with a polishing pad while a polishing slurry containing abrasive grains, and an additive of a surfactant is being supplied onto the polishing pad 104 to thereby planarize the surface of the film-to-be-polished, and the step of further polishing the surface of the film-to-be-polished with the polishing pad while the polishing slurry and water are being supplied onto the polishing pad, after the surface of the film-to-be-polished has been planarized.Type: GrantFiled: April 14, 2004Date of Patent: May 31, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Takashi Watanabe, Naoki Idani, Toshiyuki Isome
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Patent number: 7908698Abstract: A wafer on which a CMP processing is completed is rotated. A front surface cleaning brush and a rear surface cleaning brush are made contact both surfaces of the wafer while being rotated. After the front surface cleaning brush and the rear surface cleaning brush are made to contact the wafer, both end portions of the front surface cleaning brush and the rear surface cleaning brush are deformed by means of pressurizing both ends of the front surface cleaning brush and the rear surface cleaning brush by pressure portions. That is, the both end portions of the front surface cleaning brush and the rear surface cleaning brush are compressed to enlarge diameters in the both end portions. As a consequence, the entire front surface of the wafer is made to contact the front surface cleaning brush substantially evenly, even if the wafer is warped into a shape of a mound. Therefore, a cleaning efficiency of the outer peripheral portion of the wafer improves.Type: GrantFiled: April 27, 2006Date of Patent: March 22, 2011Assignee: Fujitsu Semiconductor LimitedInventor: Naoki Idani
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Patent number: 7879724Abstract: A method of manufacturing a semiconductor device has polishing a film, and cleaning a polished surface by carrying out a first exposing the polished surface to an acidic first cleaning fluid having an effect of etching at least a partial region of the polished surface, and a second exposing the polished surface to an alkaline second cleaning fluid after the first exposing.Type: GrantFiled: March 20, 2008Date of Patent: February 1, 2011Assignee: Fujitsu Semiconductor LimitedInventor: Naoki Idani
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Publication number: 20090215267Abstract: A method of manufacturing a semiconductor device includes: polishing a semiconductor substrate to expose a polysilicon film on the semiconductor substrate using a chemical mechanical polishing method; cleaning the semiconductor substrate using a first acid cleaning solution; cleaning the semiconductor substrate with an ultrasonic wave using a second cleaning solution after cleaning the semiconductor substrate with said first acid cleaning solution; and cleaning the semiconductor substrate using a third cleaning solution, which is alkaline, after cleaning the semiconductor substrate with an ultrasonic wave.Type: ApplicationFiled: February 25, 2009Publication date: August 27, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Seiichi SHIBATA, Naoki IDANI, Takashi WATANABE
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Publication number: 20090075477Abstract: According to an aspect of an embodiment, a method of manufacturing a semiconductor device has forming a silicon-containing layer over a semiconductor substrate, forming a metal layer over the semiconductor substrate and the silicon-containing layer, forming a silicide-containing layer over the semiconductor substrate and the silicon-containing layer by heat treatment of the semiconductor substrate and the silicon-containing layer, and applying flash annealing to the silicide-containing layer.Type: ApplicationFiled: September 10, 2008Publication date: March 19, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Kazuo KAWAMURA, Shinichi AKIYAMA, Kazuya OKUBO, Akira KATAKAMI, Naoki IDANI, Takashi WATANABE
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Publication number: 20090056102Abstract: A method for fabricating a semiconductor device includes (a) depositing an insulating film on a semiconductor substrate; (b) forming a recess in the insulating film; (c) depositing a conductive film on the insulating film while filling the recess with the conductive film; and (d) polishing the conductive film. Step (d) includes a first polishing substep of using a first polisher pad conditioned with a first dresser and a second polishing substep of using a second polisher pad conditioned with a second dresser different from the first dresser.Type: ApplicationFiled: August 28, 2008Publication date: March 5, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Manabu SAKAMOTO, Tetsuya SHIRASU, Naoki IDANI
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Publication number: 20080242081Abstract: A polishing method includes a first polishing step of halfway polishing a film to be polished formed on a substrate, and a second polishing step of further polishing the polished film, wherein a first film thickness profile showing an in-plane distribution of a film thickness of the polished film after the second polishing step for a first substrate is measured, and the first polishing step for a second substrate is executed to obtain a second film thickness profile which has a size relation in a film thickness opposite to the first film thickness profile.Type: ApplicationFiled: March 26, 2008Publication date: October 2, 2008Applicant: FUJITSU LIMITEDInventor: Naoki IDANI
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Publication number: 20080233753Abstract: A method of manufacturing a semiconductor device has polishing a film, and cleaning a polished surface by carrying out a first exposing the polished surface to an acidic first cleaning fluid having an effect of etching at least a partial region of the polished surface, and a second exposing the polished surface to an alkaline second cleaning fluid after the first exposing.Type: ApplicationFiled: March 20, 2008Publication date: September 25, 2008Applicant: FUJITSU LIMITEDInventor: Naoki IDANI
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Patent number: 7424688Abstract: Designing method of an electronic device subjected to a chemical mechanical polishing process in a fabrication process thereof is conducted according to the steps of: dividing a substrate surface into first sub-regions; optimizing a coverage ratio of hard-to-polish regions in the first sub-regions to fall in a first predetermined range corresponding to the first sub-regions; dividing the substrate surface into second sub-regions different from the first sub-regions; and optimizing a coverage ratio of the hard-to-polish regions in the second sub-regions to fall in a second predetermined range corresponding to the second sub-regions, wherein patterns having a shorter edge of 5 ?m or less are excluded from the optimization.Type: GrantFiled: January 18, 2006Date of Patent: September 9, 2008Assignee: Fujitsu LimitedInventors: Naoki Idani, Toshiyuki Karasawa, Ryota Nanjo