Patents by Inventor Naoki Imakita

Naoki Imakita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10245969
    Abstract: A power source control device includes a charging state detector configured to detect a charging state of a drive battery mounted on an electric vehicle and a power source mode switch configured to switch a power source mode of the electric vehicle, wherein the power source mode switch configured to switch the power source mode to an OFF mode in a case that charging of the drive battery is stopped while the power source mode is set at an ON mode.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: April 2, 2019
    Assignee: MITSUBISHI JIDOSHA KOGYO KABUSHIKI KAISHA
    Inventors: Makoto Kamachi, Takayoshi Kawamoto, Naoki Imakita, Jun Soeda, Hirofumi Yagura, Hirotaka Sugimoto
  • Publication number: 20180162230
    Abstract: A power source control device includes a charging state detector configured to detect a charging state of a drive battery mounted on an electric vehicle and a power source mode switch configured to switch a power source mode of the electric vehicle, wherein the power source mode switch configured to switch the power source mode to an OFF mode in a case that charging of the drive battery is stopped while the power source mode is set at an ON mode.
    Type: Application
    Filed: December 6, 2017
    Publication date: June 14, 2018
    Applicant: MITSUBISHI JIDOSHA KOGYO KABUSHIKI KAISHA
    Inventors: Makoto KAMACHI, Takayoshi KAWAMOTO, Naoki IMAKITA, Jun SOEDA, Hirofumi YAGURA, Hirotaka SUGIMOTO
  • Patent number: 9202784
    Abstract: A semiconductor integrated circuit device includes a substrate structure layer including a substrate having a well and a diffusion region thereon, an interconnect layer including a pair of power supply lines arranged at a preset spacing from the substrate structure layer; the interconnect layer also including an input side interconnect and an output side interconnect between the pair of power supply lines, a standard cell having a logic circuit on the substrate; the logic circuit being electrically connected to the pair of power supply lines, the input side interconnect and the output side interconnect, and one or more capacitances arranged between the substrate structure layer and the interconnect layer and arranged in a region between the pair of power supply lines, the region being inclusive of a region superposed with the pair of power supply lines.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: December 1, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masatake Wada, Naoki Imakita
  • Patent number: 8546913
    Abstract: A capacitance cell includes a substrate structure layer having pair diffusion regions, and an interconnect layer having pair of power supply lines. The capacitance cell also includes a capacitance composed of a first electrode, a dielectric member and a second electrode stacked together, and is formed in a frame shape and disposed in a space between the substrate structure layer and the interconnect layer so as to extend along an outer rim of the frame shape of a standard cell region in which a standard cell is arranged. The capacitance cell also includes a first substrate contact that electrically connects one of the pair of power supply lines to one of the diffusion regions externally of the standard cell region. The capacitance cell also includes a second substrate contact that electrically connects the other power supply line to the other diffusion region, externally of the standard cell region.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: October 1, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Masatake Wada, Naoki Imakita
  • Publication number: 20130228896
    Abstract: A semiconductor integrated circuit device includes a substrate structure layer including a substrate having a well and a diffusion region thereon, an interconnect layer including a pair of power supply lines arranged at a preset spacing from the substrate structure layer; the interconnect layer also including an input side interconnect and an output side interconnect between the pair of power supply lines, a standard cell having a logic circuit on the substrate; the logic circuit being electrically connected to the pair of power supply lines, the input side interconnect and the output side interconnect, and one or more capacitances arranged between the substrate structure layer and the interconnect layer and arranged in a region between the pair of power supply lines, the region being inclusive of a region superposed with the pair of power supply lines.
    Type: Application
    Filed: April 18, 2013
    Publication date: September 5, 2013
    Applicant: Renesas Electronics Corporation
    Inventors: Masatake Wada, Naoki Imakita
  • Publication number: 20110204477
    Abstract: A capacitance cell includes a substrate structure layer having pair diffusion regions, and an interconnect layer having pair of power supply lines. The capacitance cell also includes a capacitance composed of a first electrode, a dielectric member and a second electrode stacked together, and is formed in a frame shape and disposed in a space between the substrate structure layer and the interconnect layer so as to extend along an outer rim of the frame shape of a standard cell region in which a standard cell is arranged. The capacitance cell also includes a first substrate contact that electrically connects one of the pair of power supply lines to one of the diffusion regions externally of the standard cell region. The capacitance cell also includes a second substrate contact that electrically connects the other power supply line to the other diffusion region, externally of the standard cell region.
    Type: Application
    Filed: April 1, 2011
    Publication date: August 25, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Masatake Wada, Naoki Imakita