Patents by Inventor Naoki Inagaki

Naoki Inagaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11794325
    Abstract: A power tool having a rotary hammer mechanism is configured to produce hammering motion for driving a tool accessory along a driving axis and rotating motion for rotating the tool accessory around the driving axis. The power tool has a tool holder that is configured to removably hold the tool accessory. The tool holder has a rotation transmitting part configured to transmit rotating power to the tool accessory. A layer formed of carbide of a group 5 element of a periodic table is formed on the rotation transmitting part.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: October 24, 2023
    Assignee: MAKITA CORPORATION
    Inventors: Naoki Inagaki, Yoshitaka Machida, Hiroki Kaneko
  • Publication number: 20220281092
    Abstract: A power tool having a rotary hammer mechanism is configured to produce hammering motion for driving a tool accessory along a driving axis and rotating motion for rotating the tool accessory around the driving axis. The power tool has a tool holder that is configured to removably hold the tool accessory. The tool holder has a rotation transmitting part configured to transmit rotating power to the tool accessory. A layer formed of carbide of a group 5 element of a periodic table is formed on the rotation transmitting part.
    Type: Application
    Filed: February 16, 2022
    Publication date: September 8, 2022
    Applicant: MAKITA CORPORATION
    Inventors: Naoki INAGAKI, Yoshitaka MACHIDA, Hiroki KANEKO
  • Publication number: 20210061651
    Abstract: A MEMS microphone includes: a glass substrate including an opening portion; a membrane provided on the glass substrate so as to cover the opening portion and including a first conductive layer; and a backplate provided above the membrane via a cavity, including a plurality of through holes through which sound waves pass, and including a second conductive layer. The first conductive layer is made of a metal or a conductive oxide. The second conductive layer is made of a metal or a conductive oxide.
    Type: Application
    Filed: November 11, 2020
    Publication date: March 4, 2021
    Applicant: TOPPAN PRINTING CO., LTD.
    Inventors: Yasuko GOTOH, Hiroyuki CHIKAMORI, Naohiro NOMURA, Naoki INAGAKI
  • Patent number: 10457711
    Abstract: Provided are a novel Dermatophagoides farinae protein, and a diagnostic drug, a prophylactic drug and a therapeutic drug for an allergic disease caused by Dermatophagoides farinae. A Dermatophagoides farinae protein selected from the group consisting of the following (a) to (c), or a fragment peptide thereof: (a) a protein including an amino acid sequence set forth in SEQ ID NO:2; (b) a protein including an amino acid sequence in which one or several amino acids have been substituted, deleted, or added relative to the amino acid sequence set forth in SEQ ID NO:2, and having allergenicity of Dermatophagoides farinae; and (c) a protein including an amino acid sequence having 90% or higher identity with the amino acid sequence set forth in SEQ ID NO:2, and having allergenicity of Dermatophagoides farinae.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: October 29, 2019
    Assignee: TAIHO PHARMACEUTICAL CO., LTD.
    Inventors: Naomasa Asaka, Yuki Tanaka, Naoki Inagaki
  • Publication number: 20180265556
    Abstract: Provided are a novel Dermatophagoides farinae protein, and a diagnostic drug, a prophylactic drug and a therapeutic drug for an allergic disease caused by Dermatophagoides farinae. A Dermatophagoides farinae protein selected from the group consisting of the following (a) to (c), or a fragment peptide thereof: (a) a protein including an amino acid sequence set forth in SEQ ID NO:2; (b) a protein including an amino acid sequence in which one or several amino acids have been substituted, deleted, or added relative to the amino acid sequence set forth in SEQ ID NO:2, and having allergenicity of Dermatophagoides farinae; and (c) a protein including an amino acid sequence having 90% or higher identity with the amino acid sequence set forth in SEQ ID NO:2, and having allergenicity of Dermatophagoides farinae.
    Type: Application
    Filed: December 1, 2015
    Publication date: September 20, 2018
    Applicant: TAIHO PHARMACEUTICAL CO., LTD.
    Inventors: Naomasa ASAKA, Yuki TANAKA, Naoki INAGAKI
  • Patent number: 8294655
    Abstract: A liquid crystal display apparatus to which the present invention is applied has a first data conversion circuit and a second data conversion circuit. The first data conversion circuit converts each predetermined number of display data included in prepared display data into pixel data in which the respective display data are arranged in a predetermined arranging order and in time-series. The second data conversion circuit is provided for each the predetermined number of signal lines included in the display apparatus and sequentially applies display signal voltages corresponding to the pixel data to the predetermined number of signal lines respectively. The liquid crystal display apparatus equalizes the amounts of charges to be written in respective display pixels by reversing the arranging order of the display data in the pixel data and the order of applying the display signal voltages to the signal lines per field period or per horizontal scanning period.
    Type: Grant
    Filed: February 12, 2009
    Date of Patent: October 23, 2012
    Assignee: Casio Computer Co., Ltd.
    Inventors: Ryuichi Hirayama, Shunji Kashiyama, Naoki Inagaki
  • Publication number: 20110157501
    Abstract: When a signal, which is switched between a first level (0 V) and a second level (Vseg) in a predetermined cycle, is input to a common electrode and respective segment electrodes of a plurality of polymer network (PN) liquid crystal display elements to be subjected to static driving, the plurality of PN liquid crystal display elements are divided into two or more groups. The level switching of a signal (SEG-A) that is output to the segment electrode of the PN liquid crystal display element included in one group and the level switching of a signal (SEG-B) that is output to the segment electrode of the PN liquid crystal display element as each signal output to the respective segment electrodes of the plurality of PN liquid crystal display elements are performed at timings that do not overlap each other.
    Type: Application
    Filed: December 8, 2010
    Publication date: June 30, 2011
    Applicant: CASIO COMPUTER CO., LTD.
    Inventors: Minoru USUI, Ryuichi Hirayama, Naoki Inagaki
  • Publication number: 20090146939
    Abstract: A liquid crystal display apparatus to which the present invention is applied has a first data conversion circuit and a second data conversion circuit. The first data conversion circuit converts each predetermined number of display data included in prepared display data into pixel data in which the respective display data are arranged in a predetermined arranging order and in time-series. The second data conversion circuit is provided for each the predetermined number of signal lines included in the display apparatus and sequentially applies display signal voltages corresponding to the pixel data to the predetermined number of signal lines respectively. The liquid crystal display apparatus equalizes the amounts of charges to be written in respective display pixels by reversing the arranging order of the display data in the pixel data and the order of applying the display signal voltages to the signal lines per field period or per horizontal scanning period.
    Type: Application
    Filed: February 12, 2009
    Publication date: June 11, 2009
    Applicant: Casio Computer Co., Ltd.
    Inventors: Ryuichi Hirayama, Shunji Kashiyama, Naoki Inagaki
  • Patent number: 7511691
    Abstract: A liquid crystal display apparatus to which the present invention is applied has a first data conversion circuit and a second data conversion circuit. The first data conversion circuit converts each predetermined number of display data included in prepared display data into pixel data in which the respective display data are arranged in a predetermined arranging order and in time-series. The second data conversion circuit is provided for each the predetermined number of signal lines included in the display apparatus and sequentially applies display signal voltages corresponding to the pixel data to the predetermined number of signal lines respectively. The liquid crystal display apparatus equalizes the amounts of charges to be written in respective display pixels by reversing the arranging order of the display data in the pixel data and the order of applying the display signal voltages to the signal lines per field period or per horizontal scanning period.
    Type: Grant
    Filed: December 27, 2004
    Date of Patent: March 31, 2009
    Assignee: Casio Computer Co., Ltd.
    Inventors: Ryuichi Hirayama, Shunji Kashiyama, Naoki Inagaki
  • Publication number: 20050156862
    Abstract: A liquid crystal display apparatus to which the present invention is applied has a first data conversion circuit and a second data conversion circuit. The first data conversion circuit converts each predetermined number of display data included in prepared display data into pixel data in which the respective display data are arranged in a predetermined arranging order and in time-series. The second data conversion circuit is provided for each the predetermined number of signal lines included in the display apparatus and sequentially applies display signal voltages corresponding to the pixel data to the predetermined number of signal lines respectively. The liquid crystal display apparatus equalizes the amounts of charges to be written in respective display pixels by reversing the arranging order of the display data in the pixel data and the order of applying the display signal voltages to the signal lines per field period or per horizontal scanning period.
    Type: Application
    Filed: December 27, 2004
    Publication date: July 21, 2005
    Applicant: Casio Computer Co., Ltd.
    Inventors: Ryuichi Hirayama, Shunji Kashiyama, Naoki Inagaki
  • Patent number: 6677898
    Abstract: An adaptive controller for an ESPAR antenna randomly perturbs a bias voltage vector V(n) composed of elements of bias voltage values Vm by a random vector R(n) generated by a random number generator, compares an objective function value J(n) of a cross correlation coefficient for a bias voltage vector V(n) before the perturbation with an objective function value J(n+1) of a cross correlation coefficient for a bias voltage vector V(n+1) after the perturbation, and selects and sets the bias voltage Vm corresponding to that when the cross correlation coefficient increases before and after the perturbation. Then the adaptive controller repeats the random perturbation and setting from the bias voltage of respective varactor diodes. This leads to that it is not necessary to provide a long training sequence signal, and the control process can be executed with learning so that a performance can be improved every iteration for search.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: January 13, 2004
    Assignee: Advanced Telecommunications Research Institute International
    Inventors: Jun Cheng, Akifumi Hirata, Takashi Ohira, Kyouichi Iigusa, Takuyo Nakaji, Nobuyoshi Kikuma, Naoki Inagaki
  • Publication number: 20030137451
    Abstract: An adaptive controller for an ESPAR antenna randomly perturbs a bias voltage vector V(n) composed of elements of bias voltage values Vm by a random vector R(n) generated by a random number generator, compares an objective function value J(n) of a cross correlation coefficient for a bias voltage vector V(n) before the perturbation with an objective function value J(n+1) of a cross correlation coefficient for a bias voltage vector V(n+1) after the perturbation, and selects and sets the bias voltage Vm corresponding to that when the cross correlation coefficient increases before and after the perturbation. Then the adaptive controller repeats the random perturbation and setting from the bias voltage of respective varactor diodes. This leads to that it is not necessary to provide a long training sequence signal, and the control process can be executed with learning so that a performance can be improved every iteration for search.
    Type: Application
    Filed: August 29, 2002
    Publication date: July 24, 2003
    Inventors: Jun Cheng, Akifumi Hirata, Takashi Ohira, Kyouichi Iigusa, Takuyo Nakaji, Nobuyoshi Kikuma, Naoki Inagaki
  • Patent number: 4653099
    Abstract: In an LSP sound synthesizer, LSP transform parameters for three types of sounds are prestored: human, bird, and insect. For synthesis, the inverse transform is modified to increase the quality of each type of sound: a parameter converter uses a uniform-frequency distribution (of gain) for human, a mid-frequency concentration for bird, and a high-frequency concentration for insect sounds.
    Type: Grant
    Filed: April 28, 1983
    Date of Patent: March 24, 1987
    Assignee: Casio Computer Co., Ltd.
    Inventors: Takao Kanke, Susumu Takashima, Naoki Inagaki
  • Patent number: 4578811
    Abstract: A key-in device has a key-in section with a matrix array of keys. A key-actuated signal corresponding to a handwritten character input by the key-in section is input to an input pattern memory of a character recognition section, where an input pattern is formed and stored. The character recognition section has a standard pattern memory, having stored the standard pattern of a character to be recognized. A first feature detecting section extracts feature data from the input pattern in the input pattern memory. A first matching section detects a standard pattern coincident with the feature data extracted from the first standard pattern memory, and produces the character data input by the key-in section as a recognizable character.
    Type: Grant
    Filed: September 14, 1983
    Date of Patent: March 25, 1986
    Assignee: Casio Computer Co., Ltd.
    Inventor: Naoki Inagaki
  • Patent number: 4541111
    Abstract: An LSP synthesizer (Line Spectrum Pair) includes an LSP voice synthesizer digital filter arranged for parallel operation upon voice parameters and excitation information, to obtain an LSP synthesized sound. The LSP voice synthesizer digital filter includes at least a parallel multiplier and a parallel adder. The parallel multiplier divides data into a set of upper bits and a set of lower bits and multiplies the upper and lower bits separately at specified different timings. The multiplication results are supplied to a delay circuit which adjusts timings of the multiplication results. These multiplication results are synthesized by the parallel adder to obtain a single piece of data.
    Type: Grant
    Filed: July 7, 1982
    Date of Patent: September 10, 1985
    Assignee: Casio Computer Co. Ltd.
    Inventors: Susumu Takashima, Takao Kanke, Naoki Inagaki, Kazumasa Fukushima