Patents by Inventor Naoki Kaneda

Naoki Kaneda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10354131
    Abstract: A product information outputting method includes: detecting that a hand of a person is present in a first area that is set according to a position of a product; and when the hand of the person is not detected in any one of the first area and a second area and the product is not detected in a product detection area after presence of the hand was detected based on the detecting, determining that the product has been moved out of the product detection area, the second area containing the first area, the product detection area set according to the position.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: July 16, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Shohei Kuwabara, Fumito Ito, Sayaka Suwa, Naoki Kaneda
  • Patent number: 10340345
    Abstract: A nitride semiconductor epitaxial wafer includes a substrate, a GaN layer provided over the substrate, and an AlGaN layer provided over the GaN layer. The GaN layer has a wurtzite crystal structure, and a ratio c/a of a lattice constant c in a c-axis orientation of the GaN layer to a lattice constant a in an a-axis orientation of the GaN layer is not more than 1.6266.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: July 2, 2019
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Takeshi Tanaka, Naoki Kaneda, Yoshinobu Narita
  • Patent number: 9899570
    Abstract: There is provided a semiconductor multilayer structure, including: an n-type GaN layer; and a p-type GaN layer which is formed on the n-type GaN layer and into which Mg is ion-implanted, and generating an electroluminescence emission having a peak at a photon energy of 3.0 eV or more, by applying a voltage to a pn-junction formed by the n-type GaN layer and the p-type GaN layer.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: February 20, 2018
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Naoki Kaneda, Tomoyoshi Mishima, Tohru Nakamura
  • Patent number: 9867534
    Abstract: According to one embodiment, an ophthalmologic apparatus is configured such that an operation unit is attached thereto. The ophthalmologic apparatus includes a measuring head, a user interface, and a controller. The measuring head is configured to perform optical measurement of a subject's eye. The user interface is used for performing an operation in relation to the optical measurement of the subject's eye. The controller is configured to detect whether an operation on the operation unit is enabled. Further, the controller is configured to perform at least display control for the user interface in different operation modes between an enabled state in which the operation on the operation unit is enabled and a disabled state in which the operation on the operation unit is disabled.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: January 16, 2018
    Assignee: TOPCON CORPORATION
    Inventors: Naoki Inuzuka, Tomohiro Sakurada, Naoki Kaneda
  • Publication number: 20170365666
    Abstract: A nitride semiconductor epitaxial wafer includes a substrate, a GaN layer provided over the substrate, and an AlGaN layer provided over the GaN layer. The GaN layer has a wurtzite crystal structure, and a ratio c/a of a lattice constant c in a c-axis orientation of the GaN layer to a lattice constant a in an a-axis orientation of the GaN layer is not more than 1.6266.
    Type: Application
    Filed: August 30, 2017
    Publication date: December 21, 2017
    Inventors: Takeshi TANAKA, Naoki KANEDA, Yoshinobu NARITA
  • Patent number: 9780175
    Abstract: A nitride semiconductor epitaxial wafer includes a substrate, a GaN layer provided over the substrate, and an AlGaN layer provided over the GaN layer. The GaN layer has a wurtzite crystal structure, and a ratio c/a of a lattice constant c in a c-axis orientation of the GaN layer to a lattice constant a in an a-axis orientation of the GaN layer is not more than 1.6266.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: October 3, 2017
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Takeshi Tanaka, Naoki Kaneda, Yoshinobu Narita
  • Publication number: 20170141270
    Abstract: There is provided a semiconductor multilayer structure, including: an n-type GaN layer; and a p-type GaN layer which is formed on the n-type GaN layer and into which Mg is ion-implanted, and generating an electroluminescence emission having a peak at a photon energy of 3.0 eV or more, by applying a voltage to a pn-junction formed by the n-type GaN layer and the p-type GaN layer.
    Type: Application
    Filed: June 5, 2015
    Publication date: May 18, 2017
    Applicant: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Naoki KANEDA, Tomoyoshi MISHIMA, Tohru NAKAMURA
  • Publication number: 20170061491
    Abstract: A product information display system includes: a sensor; a first display; a second display; and a processor. The processor is configured to: perform a first start of displaying, on the first display, first information related to a specific product specified in accordance with an attribute of a person detected by the sensor; and perform a second start of displaying, on the second display, second information related to the specific product when it is detected that a behavior of the detected person indicates a predetermined behavior after the first start of display.
    Type: Application
    Filed: November 11, 2016
    Publication date: March 2, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Shohei Kuwabara, Fumito Ito, Sayaka Suwa, Naoki Kaneda
  • Publication number: 20170061204
    Abstract: A product information outputting method includes: detecting that a hand of a person is present in a first area that is set according to a position of a product; and when the hand of the person is not detected in any one of the first area and a second area and the product is not detected in a product detection area after presence of the hand was detected based on the detecting, determining that the product has been moved out of the product detection area, the second area containing the first area, the product detection area set according to the position.
    Type: Application
    Filed: November 10, 2016
    Publication date: March 2, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Shohei Kuwabara, Fumito Ito, Sayaka Suwa, Naoki Kaneda
  • Publication number: 20170061475
    Abstract: A product information outputting method includes: performing a detection of whether a person takes a predetermined behavior toward a first product in accordance with a result sensed by a sensor; and when it is detected that the person takes the predetermined behavior based on the detection, starting projection of a video image toward a second product that is the same type as that of the first product.
    Type: Application
    Filed: November 9, 2016
    Publication date: March 2, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Shohei Kuwabara, Fumito Ito, Sayaka Suwa, Naoki Kaneda
  • Patent number: 9530858
    Abstract: Disclosed are an npn-type bipolar transistor as a nitride semiconductor device having good characteristics, and a method of manufacturing the same. A so-called pn epitaxial substrate has a structure wherein an n-type collector layer and a p-type base layer of a three-layer structure are provided over a substrate. The three-layer structure includes first (lower layer side), second, and third (upper layer side) p-type base layers which differ in thickness and p-type impurity concentration. In a partial region inside the second p-type base layer located as an intermediate layer in the p-type base layer of the three-layer structure, an n-type emitter region is formed by ion implantation.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: December 27, 2016
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Akihisa Terano, Tomonobu Tsuchiya, Naoki Kaneda, Tomoyoshi Mishima
  • Publication number: 20160317022
    Abstract: According to one embodiment, an ophthalmologic apparatus is configured such that an operation unit is attached thereto. The ophthalmologic apparatus includes a measuring head, a user interface, and a controller. The measuring head is configured to perform optical measurement of a subject's eye. The user interface is used for performing an operation in relation to the optical measurement of the subject's eye. The controller is configured to detect whether an operation on the operation unit is enabled. Further, the controller is configured to perform at least display control for the user interface in different operation modes between an enabled state in which the operation on the operation unit is enabled and a disabled state in which the operation on the operation unit is disabled.
    Type: Application
    Filed: April 18, 2016
    Publication date: November 3, 2016
    Applicant: TOPCON CORPORATION
    Inventors: Naoki INUZUKA, Tomohiro SAKURADA, Naoki KANEDA
  • Patent number: 9184244
    Abstract: A high voltage gallium nitride based semiconductor device includes an n-type gallium nitride freestanding substrate, and an n-type gallium nitride based semiconductor layer including a drift layer formed on the surface of the n-type gallium nitride freestanding substrate so as to have a reverse breakdown voltage of not less than 3000 V. The drift layer is configured such that a carbon concentration is not less than 3.0×1016/cm3 in a region which has an electric field intensity of not more than 1.5 MV/cm when a maximum allowable voltage where there occurs no breakdown phenomenon is applied as a reverse bias voltage.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: November 10, 2015
    Assignee: Sciocs Company Limited
    Inventor: Naoki Kaneda
  • Publication number: 20150243736
    Abstract: A high voltage gallium nitride based semiconductor device includes an n-type gallium nitride freestanding substrate, and an n-type gallium nitride based semiconductor layer including a drift layer formed on the surface of the n-type gallium nitride freestanding substrate so as to have a reverse breakdown voltage of not less than 3000 V. The drift layer is configured such that a carbon concentration is not less than 3.0×1016/cm3 in a region which has an electric field intensity of not more than 1.5 MV/cm when a maximum allowable voltage where there occurs no breakdown phenomenon is applied as a reverse bias voltage.
    Type: Application
    Filed: September 9, 2014
    Publication date: August 27, 2015
    Inventor: Naoki KANEDA
  • Publication number: 20150179780
    Abstract: Disclosed are an npn-type bipolar transistor as a nitride semiconductor device having good characteristics, and a method of manufacturing the same. A so-called pn epitaxial substrate has a structure wherein an n-type collector layer and a p-type base layer of a three-layer structure are provided over a substrate. The three-layer structure includes first (lower layer side), second, and third (upper layer side) p-type base layers which differ in thickness and p-type impurity concentration. In a partial region inside the second p-type base layer located as an intermediate layer in the p-type base layer of the three-layer structure, an n-type emitter region is formed by ion implantation.
    Type: Application
    Filed: December 24, 2014
    Publication date: June 25, 2015
    Inventors: Akihisa TERANO, Tomonobu TSUCHIYA, Naoki KANEDA, Tomoyoshi MISHIMA
  • Patent number: 9059328
    Abstract: A nitride semiconductor element having a high reverse breakdown voltage and a method of manufacturing the same are provided. A diode (a vertical-type SBD) has an n?-type nitride semiconductor layer (a drift region) formed on an n-type nitride semiconductor substrate, a p-type nitride semiconductor layer formed on the n?-type nitride semiconductor layer, and besides, an anode electrode formed on the p-type nitride semiconductor layer. The p-type nitride semiconductor layer has a relatively-thin first portion and a relatively-thick second portion provided so as to surround the first portion as being in contact with an outer circumference of the first portion. Also, the relatively-thin first portion of the p-type nitride semiconductor layer is formed thinner than the second portion so as to be depleted. The relatively-thick second portion of the p-type nitride semiconductor layer forms a guard ring part.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: June 16, 2015
    Assignee: Hitachi Metals, Ltd.
    Inventors: Akihisa Terano, Kazuhiro Mochizuki, Tomonobu Tsuchiya, Tadayoshi Tsuchiya, Naoki Kaneda, Tomoyoshi Mishima
  • Patent number: 9013026
    Abstract: There is provided a group III nitride semiconductor crystal, containing a donor-type impurity and having a hydrogen concentration of 2.0E+16 cm?3 or less in a crystal.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: April 21, 2015
    Assignee: Hitachi Metals, Ltd.
    Inventors: Tadayoshi Tsuchiya, Naoki Kaneda
  • Patent number: 8835930
    Abstract: A gallium nitride rectifying device includes a p-type gallium nitride based semiconductor layer and an n-type gallium nitride based semiconductor layer, the two layers forming a pn junction with each other. The p-type gallium nitride based semiconductor layer has a carrier trap (level) density of not more than 1×1018 cm?3, or the n-type gallium nitride based semiconductor layer has a carrier trap (level) density of not more than 1×1016 cm?3.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: September 16, 2014
    Assignee: Hitachi Metals, Ltd.
    Inventors: Tadayoshi Tsuchiya, Naoki Kaneda, Tomoyoshi Mishima
  • Publication number: 20140191369
    Abstract: A nitride semiconductor device includes a first nitride semiconductor layer, and an npn junction structure including a second nitride semiconductor layer of an n-type conductivity, a third nitride semiconductor layer of a p-type conductivity, and a fourth nitride semiconductor layer of an n-type conductivity layered in this order on the first nitride semiconductor layer. The third nitride semiconductor layer includes two or more uncovered regions which are uncovered with the fourth nitride semiconductor layer.
    Type: Application
    Filed: October 31, 2013
    Publication date: July 10, 2014
    Applicant: Hitachi Metals, Ltd.
    Inventors: Tadayoshi TSUCHIYA, Naoki KANEDA, Tomoyoshi MISHIMA
  • Publication number: 20140117376
    Abstract: A nitride semiconductor element having a high reverse breakdown voltage and a method of manufacturing the same are provided. A diode (a vertical-type SBD) has an n?-type nitride semiconductor layer (a drift region) formed on an n-type nitride semiconductor substrate, a p-type nitride semiconductor layer formed on the n?-type nitride semiconductor layer, and besides, an anode electrode formed on the p-type nitride semiconductor layer. The p-type nitride semiconductor layer has a relatively-thin first portion and a relatively-thick second portion provided so as to surround the first portion as being in contact with an outer circumference of the first portion. Also, the relatively-thin first portion of the p-type nitride semiconductor layer is formed thinner than the second portion so as to be depleted. The relatively-thick second portion of the p-type nitride semiconductor layer forms a guard ring part.
    Type: Application
    Filed: October 29, 2013
    Publication date: May 1, 2014
    Applicant: Hitachi Metals, Ltd.
    Inventors: Akihisa TERANO, Kazuhiro MOCHIZUKI, Tomonobu TSUCHIYA, Tadayoshi TSUCHIYA, Naoki KANEDA, Tomoyoshi MISHIMA