Abstract: In order to make it possible to simultaneously test 16 semiconductor memory ICs each having 16 I/O ports, a connecting part acting as an adapter is inserted between each of the semiconductor memory IC and a memory IC tester part. In testing a semiconductor memory IC, first, common write data for testing is simultaneously written to a large number of memory cells of the IC. For this purpose, write data from a write data generator in the memory IC tester port is written to the memory cells through an input and output change-over circuit, a write data branching circuit, and the I/O ports. Thereafter, data is read from the memory cells and supplied to an EX-OR circuit from the 16 I/O ports. The EX-OR output is supplied to an operational result data comparison and inspection unit of the memory IC tester part via the input and output change-over circuit. The value of the EX-OR output goes to a high level only when all of the read data from the 16 I/O ports are equal, and goes to a low level otherwise.

Abstract: A semiconductor memory device provided with an on-chip test circuit is disclosed. The on-chip test circuit includes a test write circuit for writing the same write data to at least two memory cells, simultaneously in a test mode, a selection circuit for simultaneously reading stored data from the above at least two memory cells and a comparison circuit for comparing data read from the at least two memory cells whose comparison output shows whether at least one of the at least two memory cells is bad, or all of the at least two memory cells are good.

Abstract: There is disclosed a semiconductor memory device having a redundant decoder units each storing a row address assigned to a defective memory cell replaced with a redundant memory cell, and a redundant state detection unit provided with an address detecting section operative to produce a first detecting signal when a row address represented by a row address signal is identical with one of the row addresses respectively stored in the redundant decoder units, and the address detecting section comprises a single bypassing transistor coupled between a first node applied with a first voltage level and a second node where the first detecting signal appears, a single bootstrapping circuit operative to supply a gate electrode of the bypassing transistor with a second voltage level higher than the first voltage level by a value slightly lower than a threshold voltage of the bypassing transistor, and a plurality of activating transistors coupled in parallel between a source of a third voltage level and the bootstrapping

Abstract: A shift register circuit, including a plurality of stages capable of preserving data bits entered from an external source and shifting the data bits from stage to stage, each of the stages being driven by phase one, phase two and phase three clock signals, each signal alternating between a first and a second logic level. The shift register circuit comprises a first transistor responsive to the phase one clock signal for transferring a new data bit of either first or second logic level, a series combination of second, third, fourth and fifth transistors, and an output node provided between the third and fourth transistors. The second and third transistors are responsive to the new data bit transferred through the first transistor and the phase two clock signal, respectively, to place the phase three clock signal with the logic level corresponding to that of the new data bit at the output node.