Patents by Inventor Naoki Kawanabe

Naoki Kawanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10163740
    Abstract: A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: December 25, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Bunji Yasumura, Fumio Tsuchiya, Hisanori Ito, Takuji Ide, Naoki Kawanabe, Masanao Sato
  • Publication number: 20180040521
    Abstract: A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad.
    Type: Application
    Filed: October 17, 2017
    Publication date: February 8, 2018
    Inventors: Bunji YASUMURA, Fumio TSUCHIYA, Hisanori ITO, Takuji IDE, Naoki KAWANABE, Masanao SATO
  • Patent number: 9824944
    Abstract: A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: November 21, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Bunji Yasumura, Fumio Tsuchiya, Hisanori Ito, Takuji Ide, Naoki Kawanabe, Masanao Sato
  • Publication number: 20170018470
    Abstract: A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad.
    Type: Application
    Filed: September 29, 2016
    Publication date: January 19, 2017
    Inventors: Bunji YASUMURA, Fumio TSUCHIYA, Hisanori ITO, Takuji IDE, Naoki KAWANABE, Masanao SATO
  • Patent number: 9508678
    Abstract: A method of manufacturing a semiconductor device which improves the reliability of a semiconductor device. The method of manufacturing the semiconductor device includes the step of connecting a ball portion formed at the tip of a wire with a pad (electrode pad) of a semiconductor chip. The pad is comprised of an aluminum-based material and has a trench in its portion to be connected with the ball portion. The ball portion is comprised of a harder material than gold. The step of connecting the ball portion includes the step of applying ultrasonic waves to the ball portion.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: November 29, 2016
    Assignee: Renesas Electronics Corporation
    Inventor: Naoki Kawanabe
  • Publication number: 20150228618
    Abstract: A method of manufacturing a semiconductor device which improves the reliability of a semiconductor device. The method of manufacturing the semiconductor device includes the step of connecting a ball portion formed at the tip of a wire with a pad (electrode pad) of a semiconductor chip. The pad is comprised of an aluminum-based material and has a trench in its portion to be connected with the ball portion. The ball portion is comprised of a harder material than gold. The step of connecting the ball portion includes the step of applying ultrasonic waves to the ball portion.
    Type: Application
    Filed: January 21, 2015
    Publication date: August 13, 2015
    Inventor: Naoki KAWANABE
  • Publication number: 20150137125
    Abstract: A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad.
    Type: Application
    Filed: January 5, 2015
    Publication date: May 21, 2015
    Inventors: Bunji Yasumura, Fumio Tsuchiya, Hisanori Ito, Takuji Ide, Naoki Kawanabe, Masanao Sato
  • Patent number: 8946705
    Abstract: A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: February 3, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Bunji Yasumura, Fumio Tsuchiya, Hisanori Ito, Takuji Ide, Naoki Kawanabe, Masanao Sato
  • Patent number: 8530278
    Abstract: The degree of freedom of the chip layout in a semiconductor device is improved, and improvement in packaging density is aimed at. Since it becomes possible to form the wire of two directions on the pad of a memory chip by performing the over-bonding of reverse bonding by ball bonding, an effect equivalent to continuation stitch bonding of wedge bonding can be produced by ball bonding. Hereby, the degree of freedom of a chip layout and the degree of freedom of the lead layout of substrate 3 can be improved, and the packaging density on a substrate in a chip lamination type semiconductor device (memory card) can be improved.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: September 10, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuyasu Muto, Naoki Kawanabe, Hiroshi Ono, Tamaki Wada
  • Publication number: 20110269268
    Abstract: The degree of freedom of the chip layout in a semiconductor device is improved, and improvement in packaging density is aimed at. Since it becomes possible to form the wire of two directions on the pad of a memory chip by performing the over-bonding of reverse bonding by ball bonding, an effect equivalent to continuation stitch bonding of wedge bonding can be produced by ball bonding. Hereby, the degree of freedom of a chip layout and the degree of freedom of the lead layout of substrate 3 can be improved, and the packaging density on a substrate in a chip lamination type semiconductor device (memory card) can be improved.
    Type: Application
    Filed: July 8, 2011
    Publication date: November 3, 2011
    Inventors: NOBUYASU MUTO, Naoki Kawanabe, Hiroshi Ono, Tamaki Wada
  • Patent number: 7981788
    Abstract: The degree of freedom of the chip layout in a semiconductor device is improved, and improvement in packaging density is aimed at. Since it becomes possible to form the wire of two directions on the pad of a memory chip by performing the over-bonding of reverse bonding by ball bonding, an effect equivalent to continuation stitch bonding of wedge bonding can be produced by ball bonding. Hereby, the degree of freedom of a chip layout and the degree of freedom of the lead layout of substrate 3 can be improved, and the packaging density on a substrate in a chip lamination type semiconductor device (memory card) can be improved.
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: July 19, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuyasu Muto, Naoki Kawanabe, Hiroshi Ono, Tamaki Wada
  • Publication number: 20100295043
    Abstract: A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad.
    Type: Application
    Filed: May 12, 2010
    Publication date: November 25, 2010
    Inventors: Bunji YASUMURA, Fumio Tsuchiya, Hisanori Ito, Takuji Ide, Naoki Kawanabe, Masanao Sato
  • Patent number: 7449786
    Abstract: A semiconductor device with improved the adhesion between bonding pads and ball portions of gold wires is provided to improve the reliability of a semiconductor device. About 1 wt. % of Pd is contained in gold wires for connection between electrode pads formed on a wiring substrate and electrode pads (exposed areas of a top layer wiring formed mainly of Al) formed on a semiconductor chip. In bonded portions between the electrode and ball portions of the gold wires, an interdiffusion of Au and Al is suppressed to prevent the formation of Au4Al after PCT (Pressure Cooker Test). Thus, a desired bonding strength is obtained even when the pitch of the electrode pads is smaller than 65 ?m and the diameter of the ball portion is smaller than 55 ?m or the diameter of the wire portion of each gold wire is not larger than 25 ?m.
    Type: Grant
    Filed: February 21, 2006
    Date of Patent: November 11, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Naoki Kawanabe, Tomoo Matsuzawa, Toshiaki Morita, Takafumi Nishita
  • Publication number: 20070035002
    Abstract: The degree of freedom of the chip layout in a semiconductor device is improved, and improvement in packaging density is aimed at. Since it becomes possible to form the wire of two directions on the pad of a memory chip by performing the over-bonding of reverse bonding by ball bonding, an effect equivalent to continuation stitch bonding of wedge bonding can be produced by ball bonding. Hereby, the degree of freedom of a chip layout and the degree of freedom of the lead layout of substrate 3 can be improved, and the packaging density on a substrate in a chip lamination type semiconductor device (memory card) can be improved.
    Type: Application
    Filed: July 10, 2006
    Publication date: February 15, 2007
    Inventors: Nobuyasu Moto, Naoki Kawanabe, Hiroshi Ono, Tamaki Wada
  • Publication number: 20060138679
    Abstract: A semiconductor device with improved the adhesion between bonding pads and ball portions of gold wires is provided to improve the reliability of a semiconductor device. About 1 wt. % of Pd is contained in gold wires for connection between electrode pads formed on a wiring substrate and electrode pads (exposed areas of a top layer wiring formed mainly of Al) formed on a semiconductor chip. In bonded portions between the electrode and ball portions of the gold wires, an interdiffusion of Au and Al is suppressed to prevent the formation of Au4Al after PCT (Pressure Cooker Test). Thus, a desired bonding strength is obtained even when the pitch of the electrode pads is smaller than 65 ?m and the diameter of the ball portion is smaller than 55 ?m or the diameter of the wire portion of each gold wire is not larger than 25 ?m.
    Type: Application
    Filed: February 21, 2006
    Publication date: June 29, 2006
    Inventors: Naoki Kawanabe, Tomoo Matsuzawa, Toshiaki Morita, Takafumi Nishita
  • Patent number: 7049214
    Abstract: A method is provided to improve the adhesion between bonding pads and ball portions of gold wires to improve the reliability of a semiconductor device. About 1 wt. % of Pd is contained in gold wires for connection between electrode pads formed on a wiring substrate and electrode pads (exposed areas of a top layer wiring formed mainly of Al) formed on a semiconductor chip. In bonded portions between the electrode and ball portions of the gold wires, an interdiffusion of Au and Al is suppressed to prevent the formation of Au4Al after PCT (Pressure Cooker Test). Thus, a desired bonding strength is obtained even when the pitch of the electrode pads is smaller than 65 ?m and the diameter of the ball portion is smaller than 55 ?m or the diameter of the wire portion of each gold wire is not larger than 25 ?m.
    Type: Grant
    Filed: March 24, 2004
    Date of Patent: May 23, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Naoki Kawanabe, Tomoo Matsuzawa, Toshiaki Morita, Takafumi Nishita
  • Patent number: 7015127
    Abstract: Provided is a semiconductor device comprising a first metal film formed above a semiconductor chip, a ball portion formed over said first metal film and made of a second metal, and an alloy layer of said first metal and said second metal which alloy layer is formed between said first metal film and said ball portion, wherein said alloy layer reaches the bottom of said first metal film, and said ball portion is covered with a resin; and a manufacturing method thereof. The present invention makes it possible to improve adhesion between the bonding pad portion and ball portion of a bonding wire over an interconnect, thereby improving the reliability of the semiconductor device.
    Type: Grant
    Filed: April 8, 2003
    Date of Patent: March 21, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Yasuyuki Nakajima, Toshiaki Morita, Tomoo Matsuzawa, Seiichi Tomoi, Naoki Kawanabe
  • Publication number: 20050035449
    Abstract: A method is provided to improve adhesion between bonding pads and ball portions of gold wires to improve reliability of a semiconductor device. About 1 wt. % of Pd is contained in gold wires for connection between electrode pads formed on a wiring substrate and electrode pads (exposed areas of a top layer wiring formed mainly of Al) formed on a semiconductor chip. In bonded portions between the electrode and ball portions of the gold wires, an interdiffusion of Au and Al is suppressed to prevent the formation of Au4A1 after POT (Pressure Cooker Test). Thus, a desired bonding strength is obtained even when the pitch of the electrode pads is smaller than 65 pin and the diameter of the ball portion is smaller than 55 pm or the diameter of the wire portion of each gold wire is not larger than 25 pin.
    Type: Application
    Filed: March 24, 2004
    Publication date: February 17, 2005
    Inventors: Naoki Kawanabe, Tomoo Matsuzawa, Toshiaki Morita, Takafumi Nishita
  • Publication number: 20030168740
    Abstract: Provided is a semiconductor device comprising a first metal film formed above a semiconductor chip, a ball portion formed over said first metal film and made of a second metal, and an alloy layer of said first metal and said second metal which alloy layer is formed between said first metal film and said ball portion, wherein said alloy layer reaches the bottom of said first metal film, and said ball portion is covered with a resin; and a manufacturing method thereof. The present invention makes it possible to improve adhesion between the bonding pad portion and ball portion of a bonding wire over an interconnect, thereby improving the reliability of the semiconductor device.
    Type: Application
    Filed: February 21, 2003
    Publication date: September 11, 2003
    Inventors: Yasuyuki Nakajima, Toshiaki Morita, Tomoo Matsuzawa, Seiichi Tomoi, Naoki Kawanabe