Patents by Inventor Naoki Kitai
Naoki Kitai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9530485Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.Type: GrantFiled: August 14, 2015Date of Patent: December 27, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kenichi Osada, Koichiro Ishibashi, Yoshikazu Saitoh, Akio Nishida, Masaru Nakamichi, Naoki Kitai
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Publication number: 20150357026Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.Type: ApplicationFiled: August 14, 2015Publication date: December 10, 2015Inventors: Kenichi OSADA, Koichiro ISHIBASHI, Yoshikazu SAITOH, Akio NISHIDA, Masaru NAKAMICHI, Naoki KITAI
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Patent number: 9111636Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.Type: GrantFiled: July 3, 2014Date of Patent: August 18, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kenichi Osada, Koichiro Ishibashi, Yoshikazu Saitoh, Akio Nishida, Masaru Nakamichi, Naoki Kitai
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Publication number: 20150155031Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.Type: ApplicationFiled: July 3, 2014Publication date: June 4, 2015Inventors: Kenichi OSADA, Koichiro ISHIBASHI, Yoshikazu SAITOH, Akio NISHIDA, Masaru NAKAMICHI, Naoki KITAI
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Patent number: 8847431Abstract: A semiconductor device includes a first circuit, a second circuit, a first wire, and a pair of shield lines. The first circuit includes a voltage generating circuit generating a predetermined voltage and produces the predetermined voltage at an output end thereof. The first wire connects the output end of the first circuit to an input end of the second circuit. The pair of shield lines is disposed so as to sandwich the first wire therebetween. One of the shield lines is supplied with a power supply potential for driving at least one of the voltage generating circuit and the second circuit. Another of the shield lines is supplied with a ground potential for driving at least one of the voltage generating circuit and the second circuit.Type: GrantFiled: November 4, 2011Date of Patent: September 30, 2014Assignee: PS4 Luxco S.A.R.L.Inventors: Taihei Shido, Mototsugu Fujimitsu, Nobuhiro Oodaira, Naoki Kitai
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Patent number: 8797791Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.Type: GrantFiled: April 18, 2013Date of Patent: August 5, 2014Assignee: Renesas Electronics CorporationInventors: Kenichi Osada, Koichiro Ishibashi, Yoshikazu Saitoh, Akio Nishida, Masaru Nakamichi, Naoki Kitai
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Publication number: 20130229860Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.Type: ApplicationFiled: April 18, 2013Publication date: September 5, 2013Applicant: Renesas Electronics CorporationInventors: Kenichi Osada, Koichiro Ishibashi, Yoshikazu Saitoh, Akio Nishida, Masaru Nakamichi, Naoki Kitai
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Patent number: 8437179Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.Type: GrantFiled: June 20, 2012Date of Patent: May 7, 2013Assignee: Renesas Electronics CorporationInventors: Kenichi Osada, Koichiro Ishibashi, Yoshikazu Saitoh, Akio Nishida, Masaru Nakamichi, Naoki Kitai
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Publication number: 20120257443Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.Type: ApplicationFiled: June 20, 2012Publication date: October 11, 2012Applicant: Renesas Electronics CorporationInventors: Kenichi Osada, Koichiro Ishibashi, Yoshikazu Saitoh, Akio Nishida, Masaru Nakamichi, Naoki Kitai
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Patent number: 8232589Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.Type: GrantFiled: January 17, 2012Date of Patent: July 31, 2012Assignee: Renesas Electronics CorporationInventors: Kenichi Osada, Koichiro Ishibashi, Yoshikazu Saitoh, Akio Nishida, Masaru Nakamichi, Naoki Kitai
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Publication number: 20120112563Abstract: A semiconductor device includes a first circuit, a second circuit, a first wire, and a pair of shield lines. The first circuit includes a voltage generating circuit generating a predetermined voltage and produces the predetermined voltage at an output end thereof. The first wire connects the output end of the first circuit to an input end of the second circuit. The pair of shield lines is disposed so as to sandwich the first wire therebetween. One of the shield lines is supplied with a power supply potential for driving at least one of the voltage generating circuit and the second circuit. Another of the shield lines is supplied with a ground potential for driving at least one of the voltage generating circuit and the second circuit.Type: ApplicationFiled: November 4, 2011Publication date: May 10, 2012Applicant: Elpida Memory, Inc.Inventors: Taihei SHIDO, Mototsugu FUJIMITSU, Nobuhiro OODAIRA, Naoki KITAI
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Publication number: 20120113709Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.Type: ApplicationFiled: January 17, 2012Publication date: May 10, 2012Applicant: Renesas Electronics CorporationInventors: Kenichi Osada, Koichiro Ishibashi, Yoshikazu Saitoh, Akio Nishida, Masaru Nakamichi, Naoki Kitai
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Patent number: 8125017Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.Type: GrantFiled: May 13, 2011Date of Patent: February 28, 2012Assignee: Renesas Electronics CorporationInventors: Kenichi Osada, Koichiro Ishibashi, Yoshikazu Saitoh, Akio Nishida, Masaru Nakamichi, Naoki Kitai
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Patent number: 8031511Abstract: At the time of, for example, a set operation (SET) for making a phase-change element in a crystalline state, a pulse of a voltage Vreset required for melting the element is applied to the phase-change element, and subsequently a pulse of a voltage Vset that is lower than Vreset and is required for crystallizing the element is applied thereto. And, the magnitude of this voltage Vset is then changed depending on the ambient temperature so that the magnitude of the voltage Vset is small as the temperature becomes high (TH). In this manner, a margin of a write operation between the set operation and a reset operation (RESET) for making the element to be in amorphous state is improved.Type: GrantFiled: February 9, 2011Date of Patent: October 4, 2011Assignee: Renesas Electronics CorporationInventors: Kenichi Osada, Naoki Kitai, Takayuki Kawahara, Kazumasa Yanagisawa
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Publication number: 20110215414Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.Type: ApplicationFiled: May 13, 2011Publication date: September 8, 2011Inventors: Kenichi Osada, Koichiro Ishibashi, Yoshikazu Saitoh, Akio Nishida, Masaru Nakamichi, Naoki Kitai
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Patent number: 7964484Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.Type: GrantFiled: June 25, 2009Date of Patent: June 21, 2011Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Kenichi Osada, Koichiro Ishibashi, Yoshikazu Saitoh, Akio Nishida, Masaru Nakamichi, Naoki Kitai
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Publication number: 20110128780Abstract: At the time of, for example, a set operation (SET) for making a phase-change element in a crystalline state, a pulse of a voltage Vreset required for melting the element is applied to the phase-change element, and subsequently a pulse of a voltage Vset that is lower than Vreset and is required for crystallizing the element is applied thereto. And, the magnitude of this voltage Vset is then changed depending on the ambient temperature so that the magnitude of the voltage Vset is small as the temperature becomes high (TH). In this manner, a margin of a write operation between the set operation and a reset operation (RESET) for making the element to be in amorphous state is improved.Type: ApplicationFiled: February 9, 2011Publication date: June 2, 2011Inventors: Kenichi OSADA, Naoki Kitai, Takayuki Kawahara, Kazumasa Yanagisawa
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Patent number: 7907442Abstract: In a readout circuit (RC) which detects a difference between a change that appears on a first signal line (CBL) and a change that appears on a second signal line (CBLdm) according to stored information of each selected memory cell, the first signal line and the second signal line are separated selectively from input nodes of a data latch circuit (DL) through second MOS transistors (MN3 and MN4) and capacitively coupled to the input nodes of the data latch circuit via gates of first MOS transistors (MP1 and MP2) respectively. In this separated state, the first and second signal lines and the input nodes of the data latch circuit are precharged to different voltages, so that the gate-to-source and drain-to-source voltages of the first MOS transistors are controlled by the voltages of the first and second signal lines respectively.Type: GrantFiled: October 12, 2006Date of Patent: March 15, 2011Assignee: Renesas Electronics CorporationInventors: Naoki Kitai, Satoru Hanzawa, Akira Kotabe
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Patent number: 7907435Abstract: At the time of, for example, a set operation (SET) for making a phase-change element in a crystalline state, a pulse of a voltage Vreset required for melting the element is applied to the phase-change element, and subsequently a pulse of a voltage Vset that is lower than Vreset and is required for crystallizing the element is applied thereto. And, the magnitude of this voltage Vset is then changed depending on the ambient temperature so that the magnitude of the voltage Vset is small as the temperature becomes high (TH). In this manner, a margin of a write operation between the set operation and a reset operation (RESET) for making the element to be in amorphous state is improved.Type: GrantFiled: September 21, 2005Date of Patent: March 15, 2011Assignee: Renesas Electronics CorporationInventors: Kenichi Osada, Naoki Kitai, Takayuki Kawahara, Kazumasa Yanagisawa
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Patent number: 7692943Abstract: A semiconductor device includes a plurality of memory cells, and an error-correction circuit. Its write operation is performed by a late-write method, and ECC processing is executed in parallel with writing to shorten a cycle time. Moreover, when a memory cell is power-supplied through a well tap, the same address is not assigned while the memory cell is power-supplied through the well tap.Type: GrantFiled: December 10, 2007Date of Patent: April 6, 2010Assignees: Renesas Technology Corp., Hitachi Ulsi Systems Co., Ltd.Inventors: Kenichi Osada, Takayuki Kawahara, Ken Yamaguchi, Yoshikazu Saito, Naoki Kitai