Abstract: Based on an operation condition ?(t) of a polymer electrolyte fuel cell at a time t, the concentration distribution of a radical generation ion and the concentration distribution of a radical scavenging ion in an electrolyte membrane are estimated. Next, a load command p(t+?t) at a time (t+?t) is acquired. Next, a reference operation condition ?ref(t+?t) under which the load command p(t+?t) can be realized is acquired. Next, whether or not a judgment index exceeds a first threshold value ?1 is judged. When the judgment index exceeds ?1, an operation condition which is different from ?ref(t+?t) and gives the judgment index of ?1 or less is selected as ?(t+?t). On the other hand, when the judgment index does not exceed ?1, ?ref(t+?t) is selected as ?(t+?t). The fuel cell system has a control device for performing such treatments.

Abstract: A semiconductor device includes: a first memory cell, a second memory cell adjacent to the first memory cell, first and second write bitlines and a common bitline. The first memory cell includes: a first magnetization fixed layer, a first magnetic recording layer, a first reference layer, a first tunnel barrier film, and a first transistor. The second memory cell includes: a second magnetization fixed layer, a second magnetic recording layer, a second reference layer, a second tunnel barrier layer and a second transistor. Each of the first and second reference layer has a fixed magnetization. A common magnetization fixed layer having a fixed magnetization is coupled to the first and second magnetic recording layers. The common magnetization fixed layer and the common bitline is connected so that the common magnetization fixed layer and the common bitline are unable to be electrically unconnected.

Abstract: A semiconductor device includes: a first memory cell, a second memory cell adjacent to the first memory cell, first and second write bitlines and a common bitline. The first memory cell includes: a first magnetization fixed layer, a first magnetic recording layer, a first reference layer, a first tunnel barrier film, and a first transistor. The second memory cell includes: a second magnetization fixed layer, a second magnetic recording layer, a second reference layer, a second tunnel barrier layer and a second transistor. Each of the first and second reference layer has a fixed magnetization. A common magnetization fixed layer having a fixed magnetization is coupled to the first and second magnetic recording layers. The common magnetization fixed layer and the common bitline is connected so that the common magnetization fixed layer and the common bitline are unable to be electrically unconnected.