Abstract: The purpose of the present invention is to provide a method of purification and preparation of cultured corneal endothelial cells, and in particular, to provide cell surface markers for use in corneal endothelial cells not including transformed cells. Provided are cell markers for distinguishing normal cells and transformed cells, in particular normal and transformed corneal endothelium cells. These cell markers relate to specific cell surface markers, for example, to a normal corneal endothelial surface marker such as CD166, and a transformed cell surface marker such as CD73. By using the transformed cell surface marker such as CD73 to remove transformed cells by sorting, it becomes possible to improve purity of a normal cultured corneal endothelium. By using normal corneal endothelial surface marker such as CD166, or by combined use with the transformed cell surface marker, it becomes possible to provide a means for verifying the purity of a prepared corneal endothelium.

Abstract: A supported metal catalyst, including: a support that is a collective body of conductive particles; and dispersed active metal particles supported on the conductive particles. The conductive particles include a plurality of pores; an average entrance pore diameter of the pores is 1 to 20 nm; a standard deviation of the average entrance pore diameter is equal to or less than 50% of the average entrance pore diameter; a number fraction of the active metal particles supported in a surface layer region of the conductive particles divided by a total number of the active metal particles is equal to or more than 50%; the surface layer region is a region on a surface of the conductive particles or a region in the pores within a depth of 15 nm from the surface; and an average interparticle distance of the active metal particles is 5 to 20 nm.

Abstract: An object is to avoid a deadlock in a PLL. A PLL synthesizer includes a PLL circuit that includes a voltage control oscillation circuit configured to control an oscillation frequency according to a control voltage, an oscillation frequency storage unit configured to previously store the oscillation frequency at a first temperature, a control voltage setting unit configured to set a control voltage based on a difference between the oscillation frequency at a second temperature and the stored oscillation frequency, and a calibration processing unit configured to calibrate the voltage control oscillation circuit in a state in which the control voltage is set so that the oscillation frequency will become a predetermined frequency.

Abstract: A computer system including a first computer unit processing user's tasks, a second computer unit performing a halt operation for a virtual memory access, a main memory storing a plurality of virtual accessing data, a buffer memory unit temporarily storing a part of the virtual accessing data and having a faster operation time than that of the main memory, and a control unit controlling the above. The buffer memory unit receives a virtual memory address from the first computer unit and outputs a corresponding actual memory address for accessing the main memory. The control unit includes first and second latches and outputs a bi-state interruption signal and a multilevel interruption signal in response to states of the first and second latch circuits.