Abstract: The present invention provides a technique for treating retinal epithelium and/or nerves. More specifically, the present invention is an agent for the treatment or prevention of retinal disease or the like and/or a disease, disorder, or ophthalmological state of the nerves, the agent including at least one factor selected from the group consisting of laminin and fragments thereof, wherein the problem is solved by also providing a technique characterized in that this agent is administered together with retinal pigment epithelial cells and/or nerve cells. Specifically, the present invention can include laminin 411 (?4?1?1), laminin 511 (?5?1?1), laminin 521 (?5?2?1), or fragments of these.

Abstract: An object is to avoid a deadlock in a PLL. A PLL synthesizer includes a PLL circuit that includes a voltage control oscillation circuit configured to control an oscillation frequency according to a control voltage, an oscillation frequency storage unit configured to previously store the oscillation frequency at a first temperature, a control voltage setting unit configured to set a control voltage based on a difference between the oscillation frequency at a second temperature and the stored oscillation frequency, and a calibration processing unit configured to calibrate the voltage control oscillation circuit in a state in which the control voltage is set so that the oscillation frequency will become a predetermined frequency.

Abstract: A computer system including a first computer unit processing user's tasks, a second computer unit performing a halt operation for a virtual memory access, a main memory storing a plurality of virtual accessing data, a buffer memory unit temporarily storing a part of the virtual accessing data and having a faster operation time than that of the main memory, and a control unit controlling the above. The buffer memory unit receives a virtual memory address from the first computer unit and outputs a corresponding actual memory address for accessing the main memory. The control unit includes first and second latches and outputs a bi-state interruption signal and a multilevel interruption signal in response to states of the first and second latch circuits.