Abstract: An electrolytic capacitor includes at least one capacitor element including: an anode body including a porous part in a surface layer; a dielectric layer covering at least a part of a surface of the anode body; and a solid electrolyte layer covering at least a part of the dielectric layer. The solid electrolyte layer includes, in the anode body, a first portion disposed in a void of the porous part, and a second portion disposed outside a principal surface of the anode body. The second portion includes n or more conductive polymer layers on one principal surface of the anode body. Following relational expressions are satisfied: 18. ?m ? T ? t ? 50. ?m 9. ?m ? Tt / n ? 12.5 ?m where, n is an integer of 2 or more, and Tt is a thickness of the second portion on one principal surface of the anode body having the dielectric layer.

Abstract: A predetermined learning model is learned using an index value for a selected solution, which is a Pareto solution selected by a user among Pareto solutions based on a predetermined index, obtained from past input data including a combination of a delivery route and an additional delivery order, as training data, current input data including the combination is input to the learned predetermined learning model, a prediction index weight vector for each index of the Pareto solution is calculated, a Pareto solution in which a degree of similarity with the prediction index weight vector satisfies a predetermined condition is specified among the Pareto solutions, and the specified Pareto solution is output.

Abstract: An operating device of a human-powered vehicle comprises a base structure, a first operating member, a second operating member, a first electric switch, and a second electric switch. The base structure is mountable to the human-powered vehicle. The first operating member is pivotally coupled to the base structure about a first pivot axis. The second operating member is pivotally coupled to the base structure about a second pivot axis. The first operating member and the second operating member are arranged in a first direction. The first electric switch is at least partially provided between the first operating member and the base structure. The second electric switch is at least partially provided between the second operating member and the base structure. At least one of the first pivot axis and the second pivot axis extends along the first direction.

Abstract: A semiconductor laser device comprises a stem serving as a base; a laser diode LD submount having surface electrodes arranged thereon and joined to the surface of the stem; an LD chip joined to the surface electrode and connected with the surface electrode; and leads fixed in through holes formed in the stem by means of sealing parts and electrically connected to the surface electrodes via embedded layers in via holes formed in the LD submount, wherein grooves are formed in portions of the sealing parts or in portions of the LD submount around the connections between the leads and the embedded layers, to obtain a good modulated light waveform.

Abstract: A semiconductor device according to the present disclosure includes a base body having a first face and a second face, a lead passing through a through hole penetrating the base body and extending to a side of the first face, a sealing body filling the through hole, a dielectric substrate having a first main surface and a second main surface erected with respect to the first face, a semiconductor laser provided on a side of the first main surface of the dielectric substrate, a signal line provided on the first main surface and electrically connected to the semiconductor laser, a connecting member electrically connecting the signal line and the lead to each other, and a rear surface conductor provided on the second main surface, wherein the sealing body is provided directly below the rear surface conductor as viewed from a direction perpendicular to the first face.

Abstract: A temperature measurement method according to one embodiment includes a step of applying measurement light having a predetermined wavelength to a reflective film formed on a first surface of a substrate. Furthermore, the temperature measurement method includes a step of receiving, with an optical member, reflected light generated by the measurement light being reflected by the reflective film. Furthermore, the temperature measurement method includes a step of calculating the temperature of the substrate based on a reflectance based on the ratio between the intensity of the measurement light and the intensity of the reflected light.

Abstract: Provided are a lens, a stem, an LD chip to emit laser light with a beam center directed along a mounting surface of the stem, and a PD chip having a reflective surface formed with a dielectric multilayer film on its surface, reflecting the laser light emitted from the LD chip toward the lens, and measuring an amount of the laser light, wherein the LD chip is provided with a waveguide portion having a tip portion that is formed on a side of a front end face and has a width of 0.5 to 0.7 ?m, and having a tapered portion that is connected to the tip portion and becomes narrower toward the tip portion at a gradient of 0.018 to 0.033.

Abstract: A semiconductor laser device disclosed in this application is characterized; wherein one of the reflective surface and the secondary reflective surface is constituted by a dielectric multi-layer film that is formed on a PD chip for measuring a light quantity of the laser light; and wherein an inclination angle of the reflective surface is set to a value obtained by subtraction of a value that is less than an inclination angle of beam center, from 45 degrees, while an inclination angle of the secondary reflective surface is set to a value obtained by subtraction of a value that is more than the inclination angle of beam center, from 45 degrees.

Abstract: A semiconductor laser device comprises a stem serving as a base; a laser diode LD submount having surface electrodes arranged thereon and joined to the surface of the stem; an LD chip joined to the surface electrode and connected with the surface electrode; and leads fixed in through holes formed in the stem by means of sealing parts and electrically connected to the surface electrodes via embedded layers in via holes formed in the LD submount, wherein grooves are formed in portions of the sealing parts or in portions of the LD submount around the connections between the leads and the embedded layers, to obtain a good modulated light waveform.

Abstract: A semiconductor laser device comprises a semiconductor laser element, a photodetector to receive laser light emitted from the semiconductor laser element, and a stem on which the semiconductor laser element and the photodetector are mounted. The semiconductor laser element is disposed on a side to a stem front face between the stem front face and a farthest portion of the photodetector farthest away from the stem front face of the stem on which the semiconductor laser element and the photodetector are mounted. The photodetector has a light receiving face for receiving the laser light and a reflective film formed thereon in which part of the laser light is transmitted and the rest is reflected, the light receiving face being formed on a side facing the semiconductor laser element.

Abstract: In the present invention, in addition to arranging a plurality of amplifying elements in a staggered manner, signal path lengths from an input-side divider to gate pads of the plurality of amplifying elements are equalized, and signal path lengths from drain pads of the plurality of amplifying elements to an output-side combiner are equalized.

Abstract: A power amplifier includes: a plurality of FET cells connected in parallel to each other; a plurality of first resistors connected between gate terminals of the plurality of FET cells and grounding terminals respectively; a plurality of second resistors having one ends connected to the gate terminals of the plurality of FET cells respectively and other ends connected to each other; a plurality of capacitors connected in parallel to the plurality of second resistors respectively; and a third resistor connected between a connection point of the other ends of the plurality of second resistors and a power supply terminal, wherein the first resistors have temperature coefficients of resistance greater than those of the second and third resistors and are arranged closer to the corresponding FET cells than the third resistor.

Abstract: A power amplifier includes: a plurality of FET cells connected in parallel to each other; a plurality of first resistors connected between gate terminals of the plurality of FET cells and grounding terminals respectively; a plurality of second resistors having one ends connected to the gate terminals of the plurality of FET cells respectively and other ends connected to each other; a plurality of capacitors connected in parallel to the plurality of second resistors respectively; and a third resistor connected between a connection point of the other ends of the plurality of second resistors and a power supply terminal, wherein the first resistors have temperature coefficients of resistance greater than those of the second and third resistors and are arranged closer to the corresponding FET cells than the third resistor.

Abstract: An amplifier includes a package, a transistor chip having a gate pad and a drain pad formed elongately, the transistor chip being provided in the package, and a plurality of drain bonding wires connected to the drain pad, wherein the plurality of drain bonding wires include a first outer-most bonding wire connected to one of two end portions of the drain pad, a second outer-most bonding wire connected to the other of the two end portions of the drain pad, and an intermediate bonding wire interposed between the first outer-most bonding wire and the second outer-most bonding wire, each of the plurality of drain bonding wires is longer than 1 mm, and the first outer-most bonding wire and the second outer-most bonding wire have loop heights larger than a loop height that the intermediate bonding wire has.

Abstract: An amplifier includes a package, a transistor chip having a gate pad and a drain pad formed elongately, the transistor chip being provided in the package, and a plurality of drain bonding wires connected to the drain pad, wherein the plurality of drain bonding wires include a first outer-most bonding wire connected to one of two end portions of the drain pad, a second outer-most bonding wire connected to the other of the two end portions of the drain pad, and an intermediate bonding wire interposed between the first outer-most bonding wire and the second outer-most bonding wire, each of the plurality of drain bonding wires is longer than 1 mm, and the first outer-most bonding wire and the second outer-most bonding wire have loop heights larger than a loop height that the intermediate bonding wire has.

Abstract: In the present invention, in addition to arranging a plurality of amplifying elements in a staggered manner, signal path lengths from an input-side divider to gate pads of the plurality of amplifying elements are equalized, and signal path lengths from drain pads of the plurality of amplifying elements to an output-side combiner are equalized.

Abstract: A power amplifier includes a semiconductor substrate including transistor cells, a drain electrode for the transistor cells located on the semiconductor substrate, a drain pad located on the semiconductor substrate and connected to the drain electrode, an ion-implanted resistance located in the semiconductor substrate and extending along and in contact with the drain pad, a floating electrode located on the semiconductor substrate and in contact with the ion-implanted resistance, and an output matching circuit located outside the semiconductor substrate. The power amplifier further includes a wire connecting the drain pad to the output matching circuit.

Abstract: A transistor characteristic calculation apparatus using a large signal equivalent circuit model has a buffer trap circuit provided between a drain terminal and a source terminal such that a parallel circuit including a resistor and a capacitor, a diode, and another parallel circuit including a resistor and a capacitor are in turn connected in series.

Abstract: A transistor characteristic calculation apparatus using a large signal equivalent circuit model has a buffer trap circuit provided between a drain terminal and a source terminal such that a parallel circuit including a resistor and a capacitor, a diode, and another parallel circuit including a resistor and a capacitor are in turn connected in series.

Abstract: A semiconductor circuit substrate includes a transistor-forming substrate and a circuit-forming substrate. The transistor-forming substrate is a GaN substrate and has a Bipolar Junction Transistor (BJT) located in its top surface. The bottom surface of the transistor-forming substrate is flat and has contact regions. The circuit-forming substrate is a material other than a compound semiconductor and has no semiconductor active elements. The circuit-forming substrate has a flat top surface, contact regions buried in and exposed at the top surface, and passive circuits. The transistor-forming substrate and the circuit-forming substrate are directly bonded together without any intervening film, such as an insulating film.