Abstract: A Ni film is deposited over the entire surface of a substrate including a silicon gate. Then, the silicon gate is partially removed by, for example, CMP, thereby leaving a Ni layer having a flat upper surface and a uniform thickness directly on the silicon gate. Subsequently, silicidation is performed, thereby forming a gate electrode having a uniform silicide phase.

Abstract: In a semiconductor device, a transistor in an N-type logic region NL is covered with a tensile stress applying film and a transistor in a P-type logic region PL is covered with a compressive stress applying film. Transistors in a P-type SRAM region PS and an N-type SRAM region NS are covered with a layered film including a tensile stress applying film and a compressive stress applying film.

Abstract: A semiconductor device includes: a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; and an insulating sidewall formed on each side surface of the gate electrode. The high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the insulating sidewall. At least part of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode.

Abstract: A semiconductor device of the present invention includes, as a peripheral MIS transistor 25b, a gate insulating film 13b and a gate electrode 14b provided above an active region 10b, first and second sidewalls 19b and 23b provided on side surfaces of the gate electrode 14b, n-type source and drain regions 24b provided away from each other in the active region, nitrogen diffusion layers 18 provided below the outer sides of the gate electrode 14b, n-type extension regions 16 containing arsenic and provided in regions of the active region 10b located below the outer sides of the gate electrode 14b so that the n-type extension regions 16 cover the inner side surfaces and the bottom surfaces of the nitrogen diffusion layers 18, respectively, and n-type dopant regions 17 containing phosphorus and provided in regions of the active region 10b located below the outer sides of the gate electrode 14b and deeper than the n-type extension regions 16.

Abstract: A MISFET in a semiconductor device has a gate insulating film provided on a substrate, a gate electrode provided on the gate insulating film, sidewalls provided on the side surfaces of the gate electrode, lightly doped diffusion layers provided in the respective regions of the substrate located below the edge portions of the gate electrodes, heavily doped diffusion layers provided in the respective regions of the substrate located laterally below the gate electrode and the sidewalls, and pocket diffusion layers covering the lower portions of the lightly doped diffusion layers and parts of the side surfaces thereof in overlapping relation with each other below the gate electrode. Impurity concentrations in the pocket diffusion layers are set such that the threshold of the MISFET has a desired value.

Abstract: A semiconductor device includes a resistor element covered by a silicon oxide film. In the semiconductor device, with respective gate electrodes of MIS transistors and impurity doped layers, i.e., non-silicide regions exposed, thermal treatment for activating an impurity and silicidization are performed. Thus, auto-doping of an impurity is suppressed, so that variations in a resistance value of a resistor are suppressed. Also, the gate electrodes of the MIS transistors and the like are exposed when thermal treatment for activating an impurity, and therefore breakdown of respective gate insulation films of the MIS transistors hardly occurs.

Abstract: A semiconductor device of the present invention includes, as a peripheral MIS transistor 25b, a gate insulating film 13b and a gate electrode 14b provided above an active region 10b, first and second sidewalls 19b and 23b provided on side surfaces of the gate electrode 14b, n-type source and drain regions 24b provided away from each other in the active region, nitrogen diffusion layers 18 provided below the outer sides of the gate electrode 14b, n-type extension regions 16 containing arsenic and provided in regions of the active region 10b located below the outer sides of the gate electrode 14b so that the n-type extension regions 16 cover the inner side surfaces and the bottom surfaces of the nitrogen diffusion layers 18, respectively, and n-type dopant regions 17 containing phosphorus and provided in regions of the active region 10b located below the outer sides of the gate electrode 14b and deeper than the n-type extension regions 16.

Abstract: A mask (4) for forming active regions is formed on a surface portion of a Si layer (2) serving as a semiconductor region with a thermal oxide film (3) interposed therebetween. Dummy sidewalls (8) are formed over the side surfaces of the mask (4) for forming active regions. Then, etching is performed by using the mask (4) for forming active regions and the dummy sidewalls (8) as a mask to form trenches (9) each defining the side surfaces of the Si layer (2). Thereafter, each of the trenches (9) is filled with a plasma CVD oxide film (11), which is polished till the dummy sidewalls (8) are exposed at the surface. By removing the dummy sidewalls (8), oxidation is performed with the upper-surface edge portions of the Si layer (2) being exposed. This allows the upper-surface edge portions of the Si layer (2) to be oxidized without involving the oxidation of the lower-surface edge portions of the Si layer (2).

Abstract: A MISFET in a semiconductor device has a gate insulating film provided on a substrate, a gate electrode provided on the gate insulating film, sidewalls provided on the side surfaces of the gate electrode, lightly doped diffusion layers provided in the respective regions of the substrate located below the edge portions of the gate electrodes, heavily doped diffusion layers provided in the respective regions of the substrate located laterally below the gate electrode and the sidewalls, and pocket diffusion layers covering the lower portions of the lightly doped diffusion layers and parts of the side surfaces thereof in overlapping relation with each other below the gate electrode. Impurity concentrations in the pocket diffusion layers are set such that the threshold of the MISFET has a desired value.

Abstract: After a Si layer (2) is formed on a BOX layer (1) of a semiconductor substrate (50), trenches (11) and (15) each reaching the semiconductor substrate (50) are formed. An electric connection is provided between the Si layer (2) and an external circuit by forming a sidewall (18) composed of a conductor material over the side surfaces of the trenches (11) and (15). This facilitates fixation of the body potential of the Si layer (2). Oxidation for rounding off the upper-surface edge portions of the Si layer (2) is further performed with the upper-surface edge portions of the Si layer (2) being exposed and with the lower-surface edge portions of the Si layer (2) being covered with the sidewall (18). As a consequence, the deformation of the lower-surface edge portions of the Si layer (2) resulting from oxidation is less likely to occur and a leakage current resulting from a failure caused by the deformation of the lower-surface edge portions of the Si layer (2) is suppressed.

Abstract: A semiconductor integrated circuit includes: a logic circuit section including transistors formed on an SOI substrate; and a partially-depletion-type transistor, which is formed on the SOI substrate as a switching transistor for controlling ON/OFF states of the logic circuit section and which has a body contact portion. The partially-depletion-type transistor has a threshold voltage, which is substantially equal to that of the transistors in the logic circuit section when no potential is applied to the body contact portion and which is higher than that of the transistors in the logic circuit section when a potential is applied to the body contact portion.

Abstract: In a method for manufacturing a MIS type SOI device, when an ion-implantation is carried out to form pocket regions of an n-type MISFET, an ion-implantation mask having a mask opening and covering a body contact region of a p-type MISFET is applied, and when an ion-implantation is carried out to form pocket regions of a p-type MISFET, an ion-implantation mask having a mask opening and covering a body contact region of an n-type MISFET is applied. By preventing the impurities of the conductivity type opposite to that of the body contact region from being introduced into the pathway portion, the body electrical potential can be securely fixed.

Abstract: After a Si layer (2) is formed on a BOX layer (1) of a semiconductor substrate (50), trenches (11) and (15) each reaching the semiconductor substrate (50) are formed. An electric connection is provided between the Si layer (2) and an external circuit by forming a sidewall (18) composed of a conductor material over the side surfaces of the trenches (11) and (15). This facilitates fixation of the body potential of the Si layer (2). Oxidation for rounding off the upper-surface edge portions of the Si layer (2) is further performed with the upper-surface edge portions of the Si layer (2) being exposed and with the lower-surface edge portions of the Si layer (2) being covered with the sidewall (18). As a consequence, the deformation of the lower-surface edge portions of the Si layer (2) resulting from oxidation is less likely to occur and a leakage current resulting from a failure caused by the deformation of the lower-surface edge portions of the Si layer (2) is suppressed.

Abstract: A mask (4) for forming active regions is formed on a surface portion of a Si layer (2) serving as a semiconductor region with a thermal oxide film (3) interposed therebetween. Dummy sidewalls (8) are formed over the side surfaces of the mask (4) for forming active regions. Then, etching is performed by using the mask (4) for forming active regions and the dummy sidewalls (8) as a mask to form trenches (9) each defining the side surfaces of the Si layer (2). Thereafter, each of the trenches (9) is filled with a plasma CVD oxide film (11), which is polished till the dummy sidewalls (8) are exposed at the surface. By removing the dummy sidewalls (8), oxidation is performed with the upper-surface edge portions of the Si layer (2) being exposed. This allows the upper-surface edge portions of the Si layer (2) to be oxidized without involving the oxidation of the lower-surface edge portions of the Si layer (2).

Abstract: In a method for manufacturing a MIS type SOI device, when an ion-implantation is carried out to form pocket regions of an n-type MISFET, an ion-implantation mask having a mask opening and covering a body contact region of a p-type MISFET is applied, and when an ion-implantation is carried out to form pocket regions of a p-type MISFET, an ion-implantation mask having a mask opening and covering a body contact region of an n-type MISFET is applied. By preventing the impurities of the conductivity type opposite to that of the body contact region from being introduced into the pathway portion, the body electrical potential can be securely fixed.

Abstract: After an oxide film has been completely removed from the surface of a substrate by dip etching, the substrate is inserted into a furnace at a temperature as low as about 400° C. to deposit an amorphous silicon film thereon with almost no oxide film existing therebetween. The amorphous silicon film is then patterned into a base electrode and a dopant contained in the base electrode is diffused into the substrate through annealing to form an extrinsic base diffused layer. Thereafter, an intrinsic base diffused layer is formed by ion implantation and an emitter diffused layer is formed by diffusing a dopant from an emitter electrode. Since an oxide film existing between the base electrode and the substrate can be thinner, excessive expansion of the extrinsic base diffused layer due to the diffusion of the dopant can be suppressed.

Abstract: A semiconductor integrated circuit includes: a logic circuit section including transistors formed on an SOI substrate; and a partially-depletion-type transistor, which is formed on the SOI substrate as a switching transistor for controlling ON/OFF states of the logic circuit section and which has a body contact portion. The partially-depletion-type transistor has a threshold voltage, which is substantially equal to that of the transistors in the logic circuit section when no potential is applied to the body contact portion and which is higher than that of the transistors in the logic circuit section when a potential is applied to the body contact portion.

Abstract: On a main surface of a p-type silicon substrate having a bipolar transistor forming region and a MOS transistor forming region, an epitaxial layer is grown and n-type buried layers are formed. After forming a trench penetrating the buried layer, a buried polysilicon layer is formed in the trench. Then, a threshold control layer, a punch-through stopper layer, a channel stopper layer, an n-type well layer and a p-type well layer of each MOSFET are formed. At this point, since the well layer is formed through high energy ion implantation, the n-type buried layer is suppressed from being enlarged, and hence, time required for forming the trench can be shortened. Thus, a practical method of manufacturing a semiconductor device is provided.

Abstract: On a main surface of a p-type silicon substrate having a bipolar transistor forming region and a MOS transistor forming region, an epitaxial layer is grown and n-type buried layers are formed. After forming a trench penetrating the buried layer, a buried polysilicon layer is formed in the trench. Then, a threshold control layer, a punch-through stopper layer, a channel stopper layer, an n-type well layer and a p-type well layer of each MOSFET are formed. At this point, since the well layer is formed through high energy ion implantation, the n-type buried layer is suppressed from being enlarged, and hence, time required for forming the trench can be shortened. Thus, a practical method of manufacturing a semiconductor device is provided.