Abstract: According to one embodiment, an electronic apparatus includes a housing, a panel, a back light, a sheet and a plurality of frame parts. The panel is within the housing. The back light emits light toward the panel. The sheet is between the panel and the back light. The frame parts are spaced apart from each other between the panel and the sheet.

Abstract: According to one embodiment, an electronic apparatus includes a housing which includes a front bezel. A display panel and a middle frame are contained in the housing. The middle frame includes a support face which supports an outer circumferential part of the display panel, and is configured to sandwich and hold the outer circumferential part of the display panel between the support face and the front bezel. A reinforcing member is attached to the middle frame. The reinforcing member reinforces the middle frame and is fixed to the front bezel through a connecting member.

Abstract: In a second system that generates a clock signal that is synchronized with a first system, a control voltage value that controls the second oscillator such that the second system is synchronized with the first system is monitored according to the phase difference between a reference signal that is generated using the output of a first oscillator in the first system and the output of a second oscillator, whereby frequency fluctuation that occurs due to age deterioration of the first oscillator is detected.

Abstract: In a second system that generates a clock signal that is synchronized with a first system, a control voltage value that controls the second oscillator such that the second system is synchronized with the first system is monitored according to the phase difference between a reference signal that is generated using the output of a first oscillator in the first system and the output of a second oscillator, whereby frequency fluctuation that occurs due to age deterioration of the first oscillator is detected.

Abstract: According to one embodiment, a video image signal processing apparatus includes a device main body which displays a video image that corresponds to a received video image signal, an HDD unit having formed therein an operating piece elastically deformed to enable a push operation of an operating component, a stand supporting the device main body while a video image display screen is erected, and having a housing section which removably houses the HDD unit, and also having an operator which elastically deforms the operating piece at a position opposed to the operating piece of the HDD unit to make the operating component operable.

Abstract: According to one embodiment, there is provided a video signal processing apparatus including an apparatus main body which performs predetermined signal processing to a received video signal to display the video signal and a stand which is placed on a predetermined base and supports the apparatus main body to upright stand a video display screen, the stand having an HDD to be connected to a signal processing unit in the apparatus main body to enable to transmit the video signal between the HDD and the signal processing unit.

Abstract: According to one embodiment, there is provided a video signal processing apparatus including an apparatus main body which performs predetermined signal processing to a received video signal to display the video signal, an HDD unit which incorporates an HDD therein, and a stand which is placed on a predetermined base and supports the apparatus main body so as to upright stand a video display screen, the stand having a storing unit which attachably/detachably stores the HDD unit in the stand.

Abstract: A frequency synchronous apparatus includes a switch, frequency division circuit, phase comparison circuit, frequency adjustment and calculation circuit, memory, conversion circuit, and voltage-controlled oscillator. The switch selects either one of a highly stable clock output and a reference clock output in accordance with a mode switching signal. The frequency division circuit divides the frequency of the synchronous clock. The phase comparison circuit detects the phase difference between an output clock from the frequency division circuit and an output clock from the switch, and outputs a phase difference value. The frequency adjustment and calculation circuit performs synchronous control so as to adjust the phase difference value output from the phase comparison circuit to 0, and outputs a synchronous control value at this time. The memory holds the synchronous control value output from the frequency adjustment and calculation circuit.

Abstract: A frequency synchronous apparatus includes a switch, frequency division circuit, phase comparison circuit, frequency adjustment and calculation circuit, memory, conversion circuit, and voltage-controlled oscillator. The switch selects either one of a highly stable clock output and a reference clock output in accordance with a mode switching signal. The frequency division circuit divides the frequency of the synchronous clock. The phase comparison circuit detects the phase difference between an output clock from the frequency division circuit and an output clock from the switch, and outputs a phase difference value. The frequency adjustment and calculation circuit performs synchronous control so as to adjust the phase difference value output from the phase comparison circuit to 0, and outputs a synchronous control value at this time. The memory holds the synchronous control value output from the frequency adjustment and calculation circuit.

Abstract: A clock synchronization system is constituted by first and second clock generating sections. The first and second clock generating units are alternately set in current and spare use modes. The apparatus clock from one clock generating section in the current use mode is supplied to an external circuit. In each clock generating section, a state signal generating section receives a first state signal representing one of the modes, and outputs a second state signal representing a set mode opposite to the mode represented by the first state signal to the other clock generating section. A clock generating section generates a clock synchronized with the network sync signal.