Abstract: Disclosed here is a data processor provided with an addressing mode for calculating each effective address from the displacement (reference address) included in the subject instruction and the information retained in an index register allocated to a general-purpose register so as to minimize an increase of the logical/physical scale. The value in the index register is increased so as to be shifted according to the memory access size, for example, by one when the memory access size is byte and by two when the memory access size is word. Because both extension and shifting are included in the effective address calculation, the number of instructions, as well as the number of execution states are reduced. And, because the array size is smaller than the address space size, the upper part of each general-purpose register is used as a data register, thereby the data amount to be written in each general-purpose register is increased and the number of times for reading/writing from/in the subject memory is reduced.

Abstract: No matter how large or small a data capacity in an address space is, code efficiency and data processing performance are improved without deteriorating the usage comfort of a CPU. Since a data processor is configured employing an instruction control unit (CONT) capable of changing interpretation of identical instructions according to dynamic switching of operation modes, dynamic switching can be made between the operation mode that limits data areas in an address space to give higher priority to higher code efficiency and quicker instruction fetch, and the operation mode that eliminates limitations on usable data areas to the fullest extent possible. Thereby, the advantages of instructions of contracted form and the like can be offered without deteriorating the usage comfort of the CPU.

Abstract: Two up-counters and two down-counters having a time difference corresponding to a dead time are provided to realize an up-down symmetric count, such that the up-counters and the down-counters are made to count the lower limit and the upper limit (a 1/2 period+the dead time), the up-counter for counting a relatively large value and the down-counter for counting a relatively large value are made to contact at the upper limit, the up-counter for counting a relatively small value and the down-counter for counting a relatively small value are made to intersect at a count value corresponding to the 1/2 period, the up-counter for counting the relatively large value and the down-counter for counting the relatively large value are made to intersect at the count value corresponding to the dead time, and the up-counter for counting the relatively small value and the down-counter for counting the relatively small value are made to contact at the lower limit.

Abstract: The invention provides a semiconductor integrated circuit device, which minimizes an increase in the physical and logical size, allows data transfers invoked by a large number of interrupts, and improves the processing efficiency. This semiconductor integrated circuit device is applied to a single chip microcomputer and includes function blocks such as CPU, data transfer controller DTC, ROM, RAMI, RAMP, timer, pulse output circuit, serial communication interface SCI, A/D converter, IOP0-11, interrupt controller, and bus controller BSC. The internal address bus IAB and the internal data bus IDB are connected to CPU, ROM, RAMI and BSC. The internal address bus PAB and the internal data bus PDB are connected to BSC, RAMP, timer, pulse output circuit, SCI, A/D converter, interrupt controller, and IOP0-11. Further, PDB is connected to DTC.

Abstract: The invention provides a semiconductor integrated circuit device, which minimizes an increase in the physical and logical size, allows data transfers invoked by a large number of interrupts, and improves the processing efficiency. This semiconductor integrated circuit device is applied to a single chip microcomputer and includes function blocks such as CPU, data transfer controller DTC, ROM, RAMI, RAMP, timer, pulse output circuit, serial communication interface SCI, A/D converter, IOP0-11, interrupt controller, and bus controller BSC. The internal address bus IAB and the internal data bus IDB are connected to CPU, ROM, RAMI and BSC. The internal address bus PAB and the internal data bus PDB are connected to BSC, RAMP, timer, pulse output circuit, SCI, A/D converter, interrupt controller, and IOP0-11. Further, PDB is connected to DTC.

Abstract: A semiconductor integrated circuit comprising a clock pulse generator, peripheral function blocks and bus master modules. The peripheral function blocks are commonly supplied with a first system clock signal of a constant frequency generated on the basis of the output from the clock pulse generator. The bus master modules are fed with a second system clock signal generated on the basis of the pulse generator output. The frequency of the second system clock signal is variable and lower than that of the first system clock signal. The function blocks supplied with the first system clock signal are connected to a data bus separate from the one connected to the function blocks fed with the second system clock signal.

Abstract: Expansion registers E0 to E7 are added to the existing general registers R0 to R7 built on-chip in a CPU 1 of 8 bits so that all the registers including the added expansion registers may be grasped in its entirety as address data to access to a memory or the like. The address operation is executed at a unit including both the expansion register and the corresponding general register. All the registers including the expansion registers are grasped as one unit of address data to handle the carry or borrow caused in the address operation. Since the expansion registers have their applications limited to the generation of address, the number of kinds or combinations of executable instructions is reduced without inviting a serious reduction in the data processing ability thereby to suppress the increase in the logical and physical scales of the CPU.The register is given 32 bits in its entirety by adding the expansion register Ei of 16 bits to the general registers RiH and RiL of 16 bits of the 8-bit CPU.

Abstract: In a semiconductor integrated circuit device having an A/D converter incorporated therein, a plurality of input channels are provided and input analog signals supplied therefrom are respectively held by a plurality of sample-to-hold circuits. The analog signals are simultaneously sampled by using such a pipeline operation that a first sampling is performed so that an analog signal held by the first sampling is A/D-converted and a second sampling is performed so that an analog signal held by the second sampling is A/D-converted, and the plurality of sample-to-hold circuits.

Abstract: Expansion registers E0 to E7 are added to the existing general registers R0 to R7 built on-chip in an 8-bit CPU (1) so that all the registers including the added expansion registers may be grasped in its entirety as address data to access to a memory or the like. The address operation is executed at a unit including both the expansion register and the corresponding general register. All the registers including the expansion registers are grasped as one unit of address data to handle the carry or borrow caused in the address operation. Since the expansion registers have their applications limited to the generation of address, the number of kinds or combinations of executable instructions is reduced without inviting a serious reduction in the data processing ability thereby to suppress the increase in the logical and physical scales of the CPU. The register is given 32 bits in its entirety by adding the expansion register Ei of 16 bits to the general registers RiH and RiL of 16 bits of the 8-bit CPU.

Abstract: A CPU has an upper compatibility with a low-order CPU to expand a continuously usable address space relatively. For latching data information, registers are constructed for being an address register with a bit number larger than the address bit number of a low-order CPU. The data information has its byte/word size specified by the size bit of an operation code. The utilization of the data information of a long word size is specified by either the prefix code or the operation code to which is newly added the same bit number as that of the low-order CPU. For the data information of the byte size, the high-/low-orders of the byte size register to be utilized are specified by predetermined 1 bit of a register specifying field. For the data information of the word size, the high-/low-orders of the word size register are specified by the predetermined 1 bit of that data information.

Abstract: A data processing apparatus comprising a central processing unit including at least one first memory bit and at least one second memory bit. The central processing unit executes an interrupting process indicated by an interruption identification signal in response to a first interruption request signal and the interruption identification signal. A first designating unit generates a designation signal indicating whether the central processing unit is in a first designating state. An interruption controller receives as input at least a plurality of second interruption request signals, a first bit state signal indicative of a state of the at least one first memory bit, a second bit state signal indicative of a state of the at least one second memory bit, and the designation signal.

Abstract: A single chip type microcomputer includes at least a central processing unit (CPU), a random-access memory (RAM), a mask read-only memory (mask ROM) and an electrically writable ROM such as an electrically erasable and programamble read-only memory (EEP-ROM). The electrically writable ROM stores both the user program and data to be preserved. The microcomputer includes further memory for storing a write control program for controlling the write operation to the writable ROM, and the electrically writable ROM and the memory are disposed to mutually different address positions on the address space of CPU. The proportion of size of the user program region and the data region in the writable ROM can be selected in a free proportion. A timer governs writes to the writable ROM.

Abstract: A single chip type microcomputer includes at least a central processing unit (CPU), a random-access memory (RAM), a mask read-only memory (mask ROM) and an electrically writable ROM such as an electrically erasable and programmable read-only memory (EEP-ROM). The electrically writable ROM stores both the user program and data to be preserved. The microcomputer includes further memory for storing a write control program for controlling the write operation to the writable ROM, and the electrically writable ROM and the memory are disposed to mutually different address positions on the address space of CPU. The proportion of size of the user program region and the data region in the writable ROM can be selected in a free proportion. A timer governs writes to the writable ROM.

Abstract: A volatile storage circuit for latching data is disposed outside a non-volatile memory array. Before a bulk erase of the memory array, some of the data items contained therein are transferred to and held by the storage circuit. The data items thus saved are rewritten to the non-volatile memory array after the bulk erase, or alternatively, on the basis of control data items transferred to the storage circuit, only regions designated by these data items are subjected to the bulk erase. Thus, in case of a bulk erase of an EEPROM, some of the stored data items can be preserved, so as to prevent illicit use of and maintain the integrity of the preserved data. Also the testing time of the data rewritten to the memory array is reduced because of the elimination of the need to test the memory area containing the preserved data in that only the integrity of the memory area containing data sourced externally need be tested.

Abstract: Non-volatile memory cells for security and a power supply voltage detection means are disposed in a non-volatile memory device. Information to be secured is stored in the security non-volatile memory cell and the output of the information to be secured which is stored in the non-volatile memory cell is inhibited by a signal from the power supply voltage detection circuit when a power supply voltage other than the rated value is applied. Accordingly, even when a power supply voltage other than the rated value is applied, the stored information of the security non-volatile memory cell can be used correctly, so that the object of improving security in the non-volatile memory device having the security function can be accomplished.

Abstract: A volatile storage circuit for latching data is disposed outside a non-volatile memory array. Before a bulk erase of the memory array, some of the data items contained therein are transferred to and held by the storage circuit. The data items thus saved are rewritten to the non-volatile memory array after the bulk erase, or alternatively, on the basis of control data items transferred to the storage circuit, only regions designated by these data items are subjected to the bulk erase. Thus, in case of a bulk erase of an EEPROM, some of the stored data items can be preserved, so as to prevent illicit use of and maintain the integrity of the preserved data. Also the testing time of the data rewritten to the memory array is reduced because of the elimination of the need to test the memory area containing the preserved data in that only the integrity of the memory area containing data sourced externally need be tested.