Abstract: Provided are a storage system and a storage control method wherein, when communication is disabled (communication via a data communication path is disabled) in spite of replacement of a second CTL among a first CTL and the second CTL that are redundant storage controllers and that are coupled via the data communication path, the first CTL executes a write process of writing dirty data and data management information to one or more storage devices while maintaining acceptance of I/O requests from a host. The replaced second CTL reads the data management information from the one or more storage devices. The first CTL stops accepting I/O requests from the host. The replaced second CTL starts accepting I/O requests from the host.

Abstract: Provided are a storage system and a storage control method wherein, when communication is disabled (communication via a data communication path is disabled) in spite of replacement of a second CTL among a first CTL and the second CTL that are redundant storage controllers and that are coupled via the data communication path, the first CTL executes a write process of writing dirty data and data management information to one or more storage devices while maintaining acceptance of I/O requests from a host. The replaced second CTL reads the data management information from the one or more storage devices. The first CTL stops accepting I/O requests from the host. The replaced second CTL starts accepting I/O requests from the host.

Abstract: A storage system according to an embodiment of the present invention includes a storage device and a storage controller having a memory chip with a magneto-resistant element as a memory element, a memory device having a memory controller for controlling the memory chip, and a processor. The processor may be configured to manage a storage are of the memory chip by dividing the storage area into a storage area used by the processor and a storage area not used by the processor. The processor may be configured to execute, in a periodic fashion, an update process of reading data stored in the storage area and writing the data back to the storage area.

Abstract: A memory device according to an embodiment of the present invention includes: a memory chip using a magnetic memory; and a memory controller that controls read/write to the memory chip. When the memory controller receives a read request from outside the memory controller, the memory controller transmits a read command to the memory chip to read data in the memory chip. The memory controller also transmits an update command to each area of the memory chip to write back the data stored in the memory chip.

Abstract: The present invention provides a storage system capable of preventing data loss when power failure or other failures occur to an external power supply, by determining whether the capacity corresponding to the write data can be saved from a volatile memory to a nonvolatile memory based on a charged capacity of a battery used as an internal power supply and a non-backed-up (not yet backed-up) data capacity from the volatile memory to the nonvolatile memory, when storing data from a host computer or a system drive to the volatile memory of the storage system. If it is determined that saving of data is possible, an area corresponding to the write data capacity is allocated in the volatile memory and data is written to the allocated area, but if it is determined that saving of data is not possible, the writing of data is suppressed.

Abstract: The present invention provides a storage system capable of preventing data loss when power failure or other failures occur to an external power supply, by determining whether the capacity corresponding to the write data can be saved from a volatile memory to a nonvolatile memory based on a charged capacity of a battery used as an internal power supply and a non-backed-up (not yet backed-up) data capacity from the volatile memory to the nonvolatile memory, when storing data from a host computer or a system drive to the volatile memory of the storage system. If it is determined that saving of data is possible, an area corresponding to the write data capacity is allocated in the volatile memory and data is written to the allocated area, but if it is determined that saving of data is not possible, the writing of data is suppressed.

Abstract: A disk subsystem and a data restoration method with which the rise time when the disk subsystem is restored can be shortened. A disk subsystem and data restoration method whereby, when the power of the disk subsystem is shut off, the shared memory management table is saved to non-volatile memory together with the cache data and, when the power of the disk subsystem is restored, the shared memory management table is referenced and the duplex data is assigned by two non-volatile memories and restored to each of two shared memories.

Abstract: A processor transmits, to a communication control module, at least one write request packet with which at least one data block element configuring a data block is respectively associated, and updates a first counter to a value corresponding to the number of the transmitted write request packets. The communication control module writes a data block element associated with the write request packet to a cache memory, updates a third counter to a value corresponding to the number of the transmitted data block elements, and reflects the third counter to a second counter. The processor determines that the data block is written to the cache memory when the second counter reaches the first counter after all write request packets are transmitted.

Abstract: A processor transmits, to a communication control module, at least one write request packet with which at least one data block element configuring a data block is respectively associated, and updates a first counter to a value corresponding to the number of the transmitted write request packets. The communication control module writes a data block element associated with the write request packet to a cache memory, updates a third counter to a value corresponding to the number of the transmitted data block elements, and reflects the third counter to a second counter. The processor determines that the data block is written to the cache memory when the second counter reaches the first counter after all write request packets are transmitted.

Abstract: A disk subsystem and a data restoration method with which the rise time when the disk subsystem is restored can be shortened. A disk subsystem and data restoration method whereby, when the power of the disk subsystem is shut off, the shared memory management table is saved to non-volatile memory together with the cache data and, when the power of the disk subsystem is restored, the shared memory management table is referenced and the duplex data is assigned by two non-volatile memories and restored to each of two shared memories.

Abstract: It is provided a storage system for storing data requested by a host computer to be written, the storage system comprising: at least one processor, a cache memory and a cache controller. The cache memory includes a first memory which can be accessed by way of either access that can specify an access range by a line or access that continuously performs a read and a write. The cache controller includes a second memory which has a higher flexibility than the first memory in specifying an access range. The cache controller determines an address of an access destination upon reception of a request for an access to the cache memory from the at least one processor, and switches a request for an access to a specific address into an access to a corresponding address in the second memory.

Abstract: It is provided a storage system for storing data requested by a host computer to be written, the storage system comprising: at least one processor, a cache memory and a cache controller. The cache memory includes a first memory which can be accessed by way of either access that can specify an access range by a line or access that continuously performs a read and a write. The cache controller includes a second memory which has a higher flexibility than the first memory in specifying an access range. The cache controller determines an address of an access destination upon reception of a request for an access to the cache memory from the at least one processor, and switches a request for an access to a specific address into an access to a corresponding address in the second memory.

Abstract: A storage system is provided with a plurality of physical storage devices and a storage control apparatus that is coupled to the plurality of physical storage devices. The storage control apparatus is provided with a first cache memory group provided with a first volatile memory and a first nonvolatile memory and a second cache memory group provided with a second volatile memory and a second nonvolatile memory. The storage control apparatus executes a double write for writing the write target data from the host device to both of the first volatile memory and the second volatile memory, and notifies the host device of the write completion in the case in which the double write is completed. The storage control apparatus backs up data from the first volatile memory to the first nonvolatile memory while an electrical power is supplied from the primary power source.

Abstract: Provided is a storage subsystem capable of maintaining the reliability of I/O processing to a host apparatus, even if there is an unauthorized access from a processor core to a switch circuit, by applying a multi-core system to a processor. A multi-core processor is applied to a second logical address space that is different from a first logical address space to be commonly applied to multiple controlled units such as a host interface to be accessed by the processor. The switch circuit determines the processor core that issued an access based on an address belonging to a second address space, and maps an address containing in an access from the processor core to an address of a first address space.

Abstract: A storage system is provided with a plurality of physical storage devices and a storage control apparatus that is coupled to the plurality of physical storage devices. The storage control apparatus is provided with a first cache memory group provided with a first volatile memory and a first nonvolatile memory and a second cache memory group provided with a second volatile memory and a second nonvolatile memory. The storage control apparatus executes a double write for writing the write target data from the host device to both of the first volatile memory and the second volatile memory, and notifies the host device of the write completion in the case in which the double write is completed. The storage control apparatus backs up data from the first volatile memory to the first nonvolatile memory while an electrical power is supplied from the primary power source.

Abstract: Provided is a storage subsystem capable of maintaining the reliability of I/O processing to a host apparatus, even if there is an unauthorized access from a processor core to a switch circuit, by applying a multi-core system to a processor. A multi-core processor is applied to a second logical address space that is different from a first logical address space to be commonly applied to multiple controlled units such as a host interface to be accessed by the processor. The switch circuit determines the processor core that issued an access based on an address belonging to a second address space, and maps an address containing in an access from the processor core to an address of a first address space.

Abstract: To provide a transceiving technology that controls the mounting area of a circuit pertaining to transmission and/or reception and where the utilization efficiency of a buffer is improved. In a transmission side circuit, there are disposed a transmission side first circuit component that generates a first packet that follows a request and a transmission side second circuit component that is a lower-level circuit component of the transmission side first circuit component, includes a transmission buffer and temporarily stores in the transmission buffer, and transmits, a second packet that includes the first packet. The second packet includes a second header portion and a second data portion. In the second data portion that the second packet that is transmitted from the transmission side second circuit component includes, there is included the first packet, and in the second header portion, there is included a predetermined value as a parameter value that represents the type of the second packet.

Abstract: Provided are a storage apparatus and its data management method capable of preventing the loss of data retained in a volatile cache memory even during an unexpected power shutdown. This storage apparatus includes a cache memory configured from a volatile and nonvolatile memory. The volatile cache memory caches data according to a write request from a host system and data staged from a disk drive, and the nonvolatile cache memory only caches data staged from a disk drive. Upon an unexpected power shutdown, the storage apparatus immediately backs up the dirty data and other information cached in the volatile cache memory to the nonvolatile cache memory.

Abstract: Proposed is a highly reliable storage apparatus with fast access speed and low power consumption, as well as a controller and control method for controlling such a storage apparatus. This storage apparatus is equipped with a flash memory that provides a storage extent for storing data, a disk-shaped memory device with more data write cycles than the flash memory, and a cache memory with faster access speed than the flash memory. Data provided from a host system is stored in the cache memory, this data is read from the cache memory at a prescribed timing, data read from the cache memory is stored in the disk-shaped memory device, and, when a prescribed condition is satisfied, this data is read from the disk-shaped memory device, and the data read from the disk-shaped memory device is stored in the flash memory.

Abstract: To provide a transceiving technology that controls the mounting area of a circuit pertaining to transmission and/or reception and where the utilization efficiency of a buffer is improved. In a transmission side circuit, there are disposed a transmission side first circuit component that generates a first packet that follows a request and a transmission side second circuit component that is a lower-level circuit component of the transmission side first circuit component, includes a transmission buffer and temporarily stores in the transmission buffer, and transmits, a second packet that includes the first packet. The second packet includes a second header portion and a second data portion. In the second data portion that the second packet that is transmitted from the transmission side second circuit component includes, there is included the first packet, and in the second header portion, there is included a predetermined value as a parameter value that represents the type of the second packet.