Patents by Inventor NAOKI MUTOU
NAOKI MUTOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11908599Abstract: A varistor includes a sintered body, an internal electrode, an insulating layer, and an external electrode. The internal electrode is disposed in an interior of the sintered body. The insulating layer covers at least part of the sintered body and includes Zn2SiO4. The external electrode is electrically connected to the internal electrode, covers part of the sintered body and part of the insulating layer, and is in contact with the part of the insulating layer. The insulating layer has a region being in contact with the external electrode, the region having a greater average thickness than a region of the insulating layer which is out of contact with the external electrode.Type: GrantFiled: August 22, 2022Date of Patent: February 20, 2024Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Keiji Kawajiri, Naoki Mutou, Hironori Motomitsu, Michiya Watanabe, Yuji Yamagishi
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Publication number: 20240013955Abstract: A multilayer varistor includes a sintered body, a first external electrode, a second external electrode, a first internal electrode, a second internal electrode, and a high-resistivity portion. The first internal electrode is provided inside the sintered body and electrically connected to the first external electrode. The second internal electrode is provided inside the sintered body and electrically connected to the second external electrode. The high-resistivity portion includes: a surface high-resistivity portion provided to cover a surface of the sintered body; and an inner high-resistivity portion extended inward from the surface high-resistivity portion inside the sintered body.Type: ApplicationFiled: November 16, 2021Publication date: January 11, 2024Inventors: Keiji KAWAJIRI, Naoki MUTOU, Hironori MOTOMITSU, Michiya WATANABE, Yuji YAMAGISHI, Yasuhiro NISHIMURA
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Patent number: 11791072Abstract: A laminated varistor includes a varistor layer, a first internal electrode provided on an upper surface of the varistor layer, a second internal electrode provided on a lower surface of the varistor layer and facing the first internal electrode across the varistor layer in upward and downward directions, a first external electrode provided on a first side surface of the varistor layer and electrically connected to the first internal electrode, and a second external electrode provided on a second side surface of the varistor layer and electrically connected to the second internal electrode. The first internal electrode is extended from the first external electrode in a first extension direction. The first internal electrode includes first electrode strips arranged in a first arrangement direction perpendicular to the first extension direction and spaced apart from one another. This laminated varistor has improved surge-resistant characteristics.Type: GrantFiled: July 16, 2020Date of Patent: October 17, 2023Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Michiya Watanabe, Naoki Mutou, Ken Yanai
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Publication number: 20230245805Abstract: A multilayer varistor according to the present disclosure includes a sintered compact, at least one pair of internal electrodes, and at least one pair of external electrodes. The sintered compact contains at least a Zn oxide and a Pr oxide. The at least one pair of internal electrodes are provided inside the sintered compact and contain, as a main component, at least one selected from the group consisting of Pd and Ag and, as a sub-component, an oxide of at least one element selected from the group consisting of Pr, Mn, Co, and Sb. The at least one pair of external electrodes are arranged to cover the sintered compact partially and electrically connected to the at least one pair of internal electrodes, respectively.Type: ApplicationFiled: January 19, 2023Publication date: August 3, 2023Inventors: Yuji YAMAGISHI, Yoshiyuki SATOU, Naoki MUTOU
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Publication number: 20230245806Abstract: A method for manufacturing a multilayer varistor includes: a first step including providing a multilayer stack in which a plurality of green sheet layers, each containing a Zn oxide powder as a main component and a Pr oxide powder as a sub-component, and a plurality of internal electrode paste layers, each containing a Pd powder, are alternately stacked; and a second step including forming a sintered compact, including an internal electrode inside, by baking the multilayer stack. The second step includes: a first sub-step including baking the multilayer stack by setting an oxygen concentration in an atmosphere at 1000 ppm by volume or less while increasing a temperature from 500° C. to 800° C.; and a second sub-step including baking, after the first sub-step, the multilayer stack by setting the oxygen concentration in the atmosphere at 1000 ppm by volume or more while increasing the temperature to a maximum allowable temperature.Type: ApplicationFiled: January 19, 2023Publication date: August 3, 2023Inventors: Naoki MUTOU, Yoshiyuki SATOU, Yuji YAMAGISHI, Ken YANAI
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Publication number: 20230081158Abstract: A varistor includes a sintered body, an internal electrode, an insulating layer, and an external electrode. The internal electrode is disposed in an interior of the sintered body. The insulating layer covers at least part of the sintered body and includes Zn2SiO4. The external electrode is electrically connected to the internal electrode, covers part of the sintered body and part of the insulating layer, and is in contact with the part of the insulating layer. The insulating layer has a region being in contact with the external electrode, the region having a greater average thickness than a region of the insulating layer which is out of contact with the external electrode.Type: ApplicationFiled: August 22, 2022Publication date: March 16, 2023Inventors: Keiji KAWAJIRI, Naoki MUTOU, Hironori MOTOMITSU, Michiya WATANABE, Yuji YAMAGISHI
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Publication number: 20220310291Abstract: A sintered body that includes semiconductor ceramic layers and an internal electrode which are alternately stacked on one another is prepared. A first external electrode is formed on a side surface of the sintered body such that the first external electrode is connected to the internal electrode. An insulating layer is formed on a surface of the sintered body by applying a glass coating over an entire of the sintered body having the formed first external electrode. The insulating layer is exposed from the first external electrode. A second external electrode is formed on the first external electrode. This method provides the produced multilayer electronic component with a stable electric connection between the internal electrodes and the external electrodes.Type: ApplicationFiled: June 13, 2022Publication date: September 29, 2022Inventors: Ken YANAI, Tomokazu YAMAGUCHI, Yuji YAMAGISHI, Naoki MUTOU, Sayaka MATSUMOTO, Ryosuke USUI
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Publication number: 20220270791Abstract: A laminated varistor includes a varistor layer, a first internal electrode provided on an upper surface of the varistor layer, a second internal electrode provided on a lower surface of the varistor layer and facing the first internal electrode across the varistor layer in upward and downward directions, a first external electrode provided on a first side surface of the varistor layer and electrically connected to the first internal electrode, and a second external electrode provided on a second side surface of the varistor layer and electrically connected to the second internal electrode. The first internal electrode is extended from the first external electrode in a first extension direction. The first internal electrode includes first electrode strips arranged in a first arrangement direction perpendicular to the first extension direction and spaced apart from one another. This laminated varistor has improved surge-resistant characteristics.Type: ApplicationFiled: July 16, 2020Publication date: August 25, 2022Inventors: MICHIYA WATANABE, NAOKI MUTOU, KEN YANAI
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Patent number: 11387023Abstract: A sintered body that includes ceramic layers and an internal electrode which are alternately stacked on one another is prepared. A first external electrode is formed on a side surface of the sintered body such that the first external electrode is connected to the internal electrode. An insulating layer is formed on a surface of the sintered body by applying a glass coating over an entire of the sintered body having the formed first external electrode. The insulating layer is exposed from the first external electrode. A second external electrode is formed on the first external electrode. This method provides the produced multilayer electronic component with a stable electric connection between the internal electrodes and the external electrodes.Type: GrantFiled: September 19, 2018Date of Patent: July 12, 2022Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Ken Yanai, Tomokazu Yamaguchi, Yuji Yamagishi, Naoki Mutou, Sayaka Matsumoto, Ryosuke Usui
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Publication number: 20200194151Abstract: A sintered body that includes semiconductor ceramic layers and an internal electrode which are alternately stacked on one another is prepared. A first external electrode is formed on a side surface of the sintered body such that the first external electrode is connected to the internal electrode. An insulating layer is formed on a surface of the sintered body by applying a glass coating over an entire of the sintered body having the formed first external electrode. The insulating layer is exposed from the first external electrode. A second external electrode is formed on the first external electrode. This method provides the produced multilayer electronic component with a stable electric connection between the internal electrodes and the external electrodes.Type: ApplicationFiled: September 19, 2018Publication date: June 18, 2020Inventors: KEN YANAI, TOMOKAZU YAMAGUCHI, YUJI YAMAGISHI, NAOKI MUTOU, SAYAKA MATSUMOTO, RYOSUKE USUI