Abstract: To provide a new data transmission system between a game device and related peripheral devices, and a device using same. Serial transmission data is divided into an odd-numbered bit sequence and an even-numbered bit sequence. Each bit of the odd-numbered bit sequence data is distributed respectively between pulses of a first pulse sequence signal having a constant interval, thereby forming a first pulse sequence signal (SDCKA). Each bit of the even-numbered bit sequence data is distributed respectively between pulses of a second pulse sequence signal having a constant interval, thereby forming a second pulse sequence signal (SDCKB). The respective time axes are adjusted such that the clock component of the first pulse sequence signal is located in the data section of the second pulse sequence signal, and the clock component of the second pulse sequence signal is located in the data section of the first pulse sequence signal.

Abstract: To provide a new data transmission system between a game device and related peripheral devices, and a device using same. Serial transmission data is divided into an odd-numbered bit sequence and an even-numbered bit sequence. Each bit of the odd-numbered bit sequence data is distributed respectively between pulses of a first pulse sequence signal having a constant interval, thereby forming a first pulse sequence signal (SDCKA). Each bit of the even-numbered bit sequence data is distributed respectively between pulses of a second pulse sequence signal having a constant interval, thereby forming a second pulse sequence signal (SDCKB). The respective time axes are adjusted such that the clock component of the first pulse sequence signal is located in the data section of the second pulse sequence signal, the clock .component of the second pulse sequence signal is located in the data section of the first pulse sequence signal.

Abstract: Serial transmission data is divided into an odd-numbered bit sequence and an even-numbered bit sequence. Each bit of the odd-numbered bit sequence data is distributed respectively between pulses of a first pulse sequence signal having a constant interval, thereby forming a first pulse sequence signal (SDCKA). Each bit of the even-numbered bit sequence data is distributed respectively between pulses of a second pulse sequence signal having a constant interval, thereby forming a second pulse sequence signal (SDCKB). The respective time axes are adjusted such that the clock component of the first pulse sequence signal is located in the data section of the second pulse sequence signal, and the clock component of the second pulse sequence signal is located in the data section of the first pulse sequence signal. Data is transmitted using these adjusted first and second pulse sequence signals (SDCKA, SDCKB).

Abstract: A data processing apparatus achieves high-speed image control, image control responding rapidly to the content of the operation of a peripheral, avoidance of possible wrong recognition of the peripheral. A subCPU is connected through a CPU bus to a main CPU which provides image control, etc. When the main CPU delivers command data to the subCPU through a register table, the subCPU determines peripheral data collection timing and collects peripheral data from the peripheral at that timing. The main CPU receives through the register table the peripheral data collected by the subCPU. The subCPU receives the peripheral data ID-1 (identification data) twice. If both the values of those peripheral data are different, the main CPU determines that the peripheral has not been connected to the peripheral port.

Abstract: A peripheral device for use with a data processing apparatus. The apparatus has a peripheral port with a set of terminal pins consisting of first to ninth pins disposed in a row. The first pin is assigned for one of a power source and the ground potential, the ninth pin for the other of the power source and the ground potential, the second, third, seventh and eighth pins for transmitting data signals, and the fourth to sixth for transmitting control signals. The apparatus has an element for selecting the communication mode of the peripheral device connected to the peripheral port, based on the data signals transmitted from the second, third, seventh and eighth pins.

Abstract: A peripheral device for use with a data processing apparatus. The apparatus has a peripheral port with a set of terminal pins consisting of first to ninth pins disposed in a row. The first pin is assigned for one of a power source and the ground potential, the ninth pin for the other of the power source and the ground potential, the second, third, seventh and eighth pins for transmitting data signals, and the fourth to sixth pins for transmitting control signals. The apparatus has an element for selecting the communication mode of the peripheral device connected to the peripheral port, based on the data signals transmitted from the second, third, seventh and eighth pins.