Patents by Inventor Naoki Ochi

Naoki Ochi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10911466
    Abstract: A network protection device includes a packet capture unit which captures a network packet through an intelligent switch which performs connection in a communication network or across communication networks; a network analyzer which detects a threat in the network packet; a threat remover which removes the threat in the network packet; and a switch operator which changes from a first communication path, which connects a sender node to a receiver node without the threat remover, to a second communication path, which is different from the first communication path and connects the sender node to the receiver node through the threat remover when the threat is detected in the threat detector.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: February 2, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Naoki Ochi, Takuji Hiramoto, Tomohiro Oda, Tatsumi Oba
  • Patent number: 10768610
    Abstract: An integration server manages production in a manufacturing line that includes a first stage and a second stage carried out after the first stage. The integration server includes a communicator that acquires a first production log and a second production log. The first production log includes a first production count of processing objects in the first stage. The second production log includes the number of processing objects in the second stage. The integration server also includes an irregularity detector that detects the presence of irregularity in the first production log and the second production log on the basis of the first production count and the number of the processing objects in the second stage.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: September 8, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Yuji Unagami, Takuji Hiramoto, Tatsumi Oba, Tomohiro Oda, Naoki Ochi
  • Publication number: 20190166139
    Abstract: A network protection device includes a packet capture unit which captures a network packet through an intelligent switch which performs connection in a communication network or across communication networks; a network analyzer which detects a threat in the network packet; a threat remover which removes the threat in the network packet; and a switch operator which changes from a first communication path, which connects a sender node to a receiver node without the threat remover, to a second communication path, which is different from the first communication path and connects the sender node to the receiver node through the threat remover when the threat is detected in the threat detector.
    Type: Application
    Filed: November 28, 2018
    Publication date: May 30, 2019
    Inventors: Naoki OCHI, Takuji HIRAMOTO, Tomohiro ODA, Tatsumi OBA
  • Publication number: 20190155258
    Abstract: An integration server manages production in a manufacturing line that includes a first stage and a second stage carried out after the first stage. The integration server includes a communicator that acquires a first production log and a second production log. The first production log includes a first production count of processing objects in the first stage. The second production log includes the number of processing objects in the second stage. The integration server also includes an irregularity detector that detects the presence of irregularity in the first production log and the second production log on the basis of the first production count and the number of the processing objects in the second stage.
    Type: Application
    Filed: October 23, 2018
    Publication date: May 23, 2019
    Inventors: YUJI UNAGAMI, TAKUJI HIRAMOTO, TATSUMI OBA, TOMOHIRO ODA, NAOKI OCHI
  • Patent number: 9535699
    Abstract: A processor includes: a first instruction processing unit that, in a first mode, receives a first input including instructions included in a first instruction set; a second instruction processing unit that, in a second mode, receives the first input, the second instruction processing unit having a simpler configuration than the first instruction processing unit; a third instruction processing unit that, in a third mode, receives a second input including instructions included in a second instruction set, the second instruction set including part of the instructions included in the first instruction set, the third instruction processing unit having a simpler configuration than the first instruction processing unit and the second instruction processing unit; a selection unit that selects, according to a mode, a result of decoding by one of the instruction processing units; and an instruction execution unit that executes an instruction according to the selected result of decoding.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: January 3, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Naoki Ochi
  • Publication number: 20140380021
    Abstract: A processor includes: a first instruction processing unit that, in a first mode, receives a first input including instructions included in a first instruction set; a second instruction processing unit that, in a second mode, receives the first input, the second instruction processing unit having a simpler configuration than the first instruction processing unit; a third instruction processing unit that, in a third mode, receives a second input including instructions included in a second instruction set, the second instruction set including part of the instructions included in the first instruction set, the third instruction processing unit having a simpler configuration than the first instruction processing unit and the second instruction processing unit; a selection unit that selects, according to a mode, a result of decoding by one of the instruction processing units; and an instruction execution unit that executes an instruction according to the selected result of decoding.
    Type: Application
    Filed: September 5, 2014
    Publication date: December 25, 2014
    Inventor: Naoki OCHI
  • Patent number: 7616429
    Abstract: Provided is an electric double layer capacitor including a large capacity single cell having a large electrostatic capacity and a small capacity single cell are connected to the same exterior case in parallel, and a thickness of a separator of the large capacity single cell is made thicker than a thickness of a separator of the small capacity single cell. With this structure, a supply amount of an electrolyte solution to the large capacity single cell is markedly increased compared with the small capacity single cell, thereby being capable of preventing degradation of the large capacity single cells and the small capacity single cells and providing the electric double layer capacitor having an excellent cycle life and having a large power storage amount while keeping characteristics capable of instantaneously allowing large current to flow.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: November 10, 2009
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenro Mitsuda, Ikuro Suga, Sadayuki Matsumoto, Makoto Seto, Naoki Ochi, Yoshiyuki Takuma
  • Publication number: 20070215926
    Abstract: Provided is an electric double layer capacitor including a large capacity single cell having a large electrostatic capacity and a small capacity single cell are connected to the same exterior case in parallel, and a thickness of a separator of the large capacity single cell is made thicker than a thickness of a separator of the small capacity single cell. With this structure, a supply amount of an electrolyte solution to the large capacity single cell is markedly increased compared with the small capacity single cell, thereby being capable of preventing degradation of the large capacity single cells and the small capacity single cells and providing the electric double layer capacitor having an excellent cycle life and having a large power storage amount while keeping characteristics capable of instantaneously allowing large current to flow.
    Type: Application
    Filed: February 28, 2007
    Publication date: September 20, 2007
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kenro Mitsuda, Ikuro Suga, Sadayuki Matsumoto, Makoto Seto, Naoki Ochi, Yoshiyuki Takuma
  • Patent number: 6191673
    Abstract: A current transformer includes transformer units combined into a bundle, each of the transformer units including an annular iron core surrounding a bus conductor and a secondary winding wound around the iron core for measuring an electric current flowing through the bus conductor, and a shield winding wound around the bundle of the transformer units. The secondary winding may be provided with an air gap in which no secondary winding is present, located at a portion of the current transformer in a direction of a resultant vector, perpendicular to a line connecting bus conductors neighboring the bus conductor to be measured and passing through the bus conductor to be measured. A second air gap may be provided at the position opposite the air gap of the transformer, relative to the bus conductor to be measured, and the shield winding may be divided into two parts at the air gap and opposite the air gap relative to the bus conductor to be measured.
    Type: Grant
    Filed: May 20, 1999
    Date of Patent: February 20, 2001
    Assignee: Mitsubushi Denki Kabushiki Kaisha
    Inventors: Shinzou Ogura, Hikozo Morisita, Naoki Ochi, Kazuhiro Nakazaki, Chiharu Umeno
  • Patent number: 5134362
    Abstract: At both ends parts of a specified section of a high tension line and close to it, a first Faraday device and a second Faraday device are disposed, and an output end of the first Faraday device is connected to the input end of the second Faraday device through a polarization plane retaining type optical fiber. A light having a linear-polarized polarization plane is inputted from a polarizer to the input end of the first Faraday device. The light output from the second Faraday device is led through an analyzer to a photoelectric device, whose output is processed by an electric circuit consisting of only one band-pass filter, only one DC filter, only one divider, and a judgment circuit.
    Type: Grant
    Filed: April 5, 1991
    Date of Patent: July 28, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Naoki Ochi
  • Patent number: 5128608
    Abstract: An optical instrument transformer can measure both current and voltage of the primary conductor. Measurement of current is made through modulation effect of a light signal by the optical magnetic-field sensor, and measurement of voltage is made through modulation effect of a light signal by the optical electric-field sensor, by measuring the voltage between a conductor member and an upper flange the of the a bushing, which has a value divided in a dividing ratio determined by the capacitance between the conductor member (4a) and the upper flange and the capacitance between the upper flange and ground.
    Type: Grant
    Filed: October 26, 1990
    Date of Patent: July 7, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Naoki Ochi
  • Patent number: 5066903
    Abstract: An optical current transformer, which uses a Faraday cell for detecting the intensity of a magnetic flux induced in a circular iron core, has plural windings having the same number of turns provided on the core in a manner that overall width of the windings are evenly wound along the whole part of the circular iron core, and terminal of the windings having the same polarities are commonly connected by cables.
    Type: Grant
    Filed: November 5, 1990
    Date of Patent: November 19, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Naoki Ochi
  • Patent number: 5059910
    Abstract: An optical transformer comprises at least two potential dividing capacitors connected in series to each other are connected between a high-voltage conductor and an intermediate electrode or between the intermediate electrode and the ground, and optical voltage sensors connected in parallel to the respective potential dividing capacitors and capable of modulating light in accordance with voltage. In another form, the optical transformer has a single potential dividing capacitor connected between a high-voltage conductor and an intermediate electrode or between the intermediate electrode and the ground, and at least two circuits connected in parallel with the potential dividing capacitor, each circuit including a series the connection of an optical voltage sensor for modulating light in accordance with the voltage and a resistor or an impedance.
    Type: Grant
    Filed: August 24, 1990
    Date of Patent: October 22, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Naoki Ochi