Abstract: A non-volatile memory apparatus is provided and includes a substrate having a major surface extending longitudinally. A stack of first and second sets of word lines and insulating layers extends along and over the major surface longitudinally and alternating with and overlying one another vertically to define a device region. The first and second sets of word lines each respectively extends longitudinally beyond a first and second side of the device region a decreasing longitudinal distance from the device region as a vertical distance from the major surface increases to define first and second stepped contact regions. Word line contacts extend vertically in the first and second stepped contact regions. The second set of word lines in the first stepped contact region do not contact the word line contacts and the first set of word lines in the second stepped contact region do not contact the word line contacts.

Abstract: A non-volatile memory device comprising a memory cell region having a plurality of co-planar memory cell planes arranged in a plane parallel to a semiconductor substrate, with each memory cell plane comprising a plurality of sub-planes disposed adjacent one another along an axis that is parallel to the substrate. Further, each memory cell plane comprises a plurality of sense amplifier regions arranged along the axis in an alternating pattern with the sub-planes such that adjacent to each sub-plane is a sense amplifier region and each sense amplifier region is operable with respect to at least a fraction of the bit lines of the two sub-planes immediately adjacent the sense amplifier region.

Abstract: A random access memory is provided including a plane structure comprising a plurality of sense amplifiers, each including a local data latch, a pair of local busses connected to each of the data latches, a differential data bus, and a pair of redrivers connected between the pair of local busses and the differential data bus.

Abstract: A non-volatile memory device comprising a memory cell region having a plurality of co-planar memory cell planes arranged in a plane parallel to a semiconductor substrate, with each memory cell plane comprising a plurality of sub-planes disposed adjacent one another along an axis that is parallel to the substrate. Further, each memory cell plane comprises a plurality of sense amplifier regions arranged along the axis in an alternating pattern with the sub-planes such that adjacent to each sub-plane is a sense amplifier region and each sense amplifier region is operable with respect to at least a fraction of the bit lines of the two sub-planes immediately adjacent the sense amplifier region.

Abstract: A non-volatile memory apparatus is provided and includes a substrate having a major surface extending longitudinally. A stack of first and second sets of word lines and insulating layers extends along and over the major surface longitudinally and alternating with and overlying one another vertically to define a device region. The first and second sets of word lines each respectively extends longitudinally beyond a first and second side of the device region a decreasing longitudinal distance from the device region as a vertical distance from the major surface increases to define first and second stepped contact regions. Word line contacts extend vertically in the first and second stepped contact regions. The second set of word lines in the first stepped contact region do not contact the word line contacts and the first set of word lines in the second stepped contact region do not contact the word line contacts.

Abstract: A random access memory is provided including a plane structure comprising a plurality of sense amplifiers, each including a local data latch, a pair of local busses connected to each of the data latches, a differential data bus, and a pair of redrivers connected between the pair of local busses and the differential data bus.

Abstract: A memory device comprising a semiconductor substrate in which a memory cell region and a peripheral circuitry region are defined, wherein the memory cell region has a plurality of non-volatile memory cells arranged in one or more arrays and the peripheral circuitry region has at least one sense amplifier region comprised of at least one low voltage transistor. Further, a deep N-well region is formed in the substrate, wherein the memory cell region and the peripheral circuitry region are placed on the deep N-well region such that, in the event that a high erase voltage (VERA) is applied to the memory cell region during an erase operation, the high erase voltage is applied to all terminals of the at least one low voltage resistor, thereby protecting the low voltage transistor by preventing it from experiencing a large voltage difference between its terminals.

Abstract: A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.

Abstract: A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.

Abstract: A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.

Abstract: A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.

Abstract: Sensing techniques and associated circuitry are provided for use with a memory device. The techniques are suited for sensing operations involving even-numbered or odd-numbered bit lines. In one approach, a mapping between caches and sense amplifiers in a sensing circuit is modified by using dual data buses. One bus is used for same-tier transfers and the other is used for cross-tier transfers. Each tier comprises a set of sense amplifiers and a corresponding set of caches. This approach does not require a modification of the input/output path which is connected to the sensing circuitry.

Abstract: Sensing techniques and associated circuitry are provided for use with a memory device. The techniques are suited for sensing operations involving even-numbered or odd-numbered bit lines. In one approach, a mapping between caches and sense amplifiers in a sensing circuit is modified by using dual data buses. One bus is used for same-tier transfers and the other is used for cross-tier transfers. Each tier comprises a set of sense amplifiers and a corresponding set of caches. This approach does not require a modification of the input/output path which is connected to the sensing circuitry.

Abstract: A semiconductor memory device includes a power supply circuit configured to supply an intermediate voltage between a power supply voltage and a ground voltage to each of a plurality of memory cells. The power supply circuit firsts generates a first intermediate voltage between the power supply voltage and the ground voltage and a second intermediate voltage between the power supply voltage and the ground voltage. In response to a first control signal, the first intermediate voltage is supplied to an output node and the second intermediate voltage stops. A connection control circuit connects the first output node and a second output node when the second intermediate voltage generating circuit stops its operation.

Abstract: A semiconductor memory device includes a power supply circuit configured to supply an intermediate voltage between a power supply voltage and a ground voltage to each of a plurality of memory cells. The power supply circuit firsts generates a first intermediate voltage between the power supply voltage and the ground voltage and a second intermediate voltage between the power supply voltage and the ground voltage. In response to a first control signal, the first intermediate voltage is supplied to an output node and the second intermediate voltage stops. A connection control circuit connects the first output node and a second output node when the second intermediate voltage generating circuit stops its operation.

Abstract: A semiconductor memory device includes: a memory cell array provided with a plurality of memory cells in a matrix; and a power supply circuit configured to supply an intermediate voltage between a power supply voltage and a ground voltage to each of the plurality of memory cells.

Abstract: A voltage generating circuit has: an operational amplifier, first to third voltage generating units, a first resistor and a second resistor. The operational amplifier generates a control signal depending on first and second voltages that are input thereto. The first voltage generating unit generates the first voltage depending on the control signal and outputs the first voltage from a first node. The second voltage generating unit generates the second voltage depending on the control signal and outputs the second voltage from a second node. The third voltage generating unit generates a third voltage as a reference voltage depending on the control signal and outputs the third voltage from a reference voltage output node. The first resistor is connected between the first node and the reference voltage output node. The second resistor connected between the second node and the reference voltage output node.

Abstract: A bandgap voltage reference circuit is provided with: a feedback circuitry, first and second PN junction elements and first and second resistor elements. The feedback circuitry provides a feedback so as to reduce a voltage between first and second nodes. The first PN junction element is connected between the first node and a ground terminal so as to allow a first current from the first node to the ground terminal to flow in a forward direction of a PN junction. The second PN junction element is connected between the first node and a ground terminal so as to allow a first current from the first node to the ground terminal to flow in a forward direction of a PN junction. The first resistor element is connected between the first node and the first PN junction element, and a second resistor element is connected between the second node and the second PN junction element.

Abstract: A semiconductor memory device includes: a memory cell array provided with a plurality of memory cells in a matrix; and a power supply circuit configured to supply an intermediate voltage between a power supply voltage and a ground voltage to each of the plurality of memory cells. The power supply circuit includes: a first intermediate voltage generating circuit configured to generate a first intermediate voltage between the power supply voltage and the ground voltage; a second intermediate voltage generating circuit configured to generate a second intermediate voltage between the power supply voltage and the ground voltage; a first output node to which the first intermediate voltage is supplied; a second output node to which the second intermediate voltage is supplied; and a connection control circuit provided between the first output node and the second output node.

Abstract: The entrapping immobilization pellets satisfy conditions: (A) the deformation rate expressed by (H0?H1)/H0×100 is 70% or more, where the thickness of the pellets before compression is H0 and the thickness of the pellets at the time the pellets are broken by compression is H1; and (B) the particle diameter falls within the range of 0.1 to 1.5 mm. The entrapping immobilization pellets are added to a biological treatment tank having no screen and the entrapping immobilization pellets discharged together with treated water to a solid-liquid separation tank are returned to the biological treatment tank by pumping. With this constitution, the entrapping immobilization pellets are less broken even if they are returned to the biological treatment tank by pumping, a conventional biological treatment tank in which wastewater is treated with activated sludge can be used without modification, and in addition, the particle diameter thereof can be reduced. Therefore, treatment efficiency can be markedly improved.