Abstract: A depth image conversion unit moves an edge location in an input depth image towards a background. A pixel shift unit generates an image from a different viewpoint by horizontally shifting coordinates of each pixel in an image based on a converted depth image. A pixel interpolation unit interpolates a missing pixel region yielded by pixel shifting.

Abstract: An image processing device (10) includes: a representative pixel value storage unit (12) which selects one of plural sub-pixels as a representative sub-pixel, and store, into a representative pixel value storage area, a representative pixel value which is a pixel value of the representative sub-pixel; and a sub-pixel value storage unit (13) which stores, into a sub-pixel value storage area, pixel values of sub-pixels other than the representative sub-pixel, wherein the sub-pixel value storage area stores one or more sets corresponding to N number of pixels, the one or more sets each including a pixel position and a pixel value of each sub-pixel other than the representative sub-pixel of a pixel at the pixel position, N being a natural number smaller than a total number of the plural pixels in the unit of processing for an edge determination unit (11).

Abstract: A plasma display system restricts peak data traffic when a shared memory is used. In the plasma display system, a control unit prohibits a moving picture decoder from accessing a shared memory while an SF reading unit is reading, from the shared memory, SF pixel data which is information about respective cells to be lit in a plurality of subfields. On the other hand, the control unit permits the moving picture decoder to access the shared memory while the SF reading unit is not reading the SF pixel data from the shared memory during a sustain discharge period.

Abstract: An image processing device (10) includes: a representative pixel value storage unit (12) which selects one of plural sub-pixels as a representative sub-pixel, and store, into a representative pixel value storage area, a representative pixel value which is a pixel value of the representative sub-pixel; and a sub-pixel value storage unit (13) which stores, into a sub-pixel value storage area, pixel values of sub-pixels other than the representative sub-pixel, wherein the sub-pixel value storage area stores one or more sets corresponding to N number of pixels, the one or more sets each including a pixel position and a pixel value of each sub-pixel other than the representative sub-pixel of a pixel at the pixel position, N being a natural number smaller than a total number of the plural pixels in the unit of processing for an edge determination unit (11).

Abstract: A depth image conversion unit 101 moves an edge location in an input depth image towards the background. A pixel shift unit 102 generates an image from a different viewpoint by horizontally shifting the coordinates of each pixel in an image based on the converted depth image. A pixel interpolation unit 103 interpolates the missing pixel region yielded by pixel shifting.

Abstract: Provided is a plasma display system capable of restricting peak data traffic when a shared memory is used. In the plasma display system, a control unit 104 prohibits a moving picture decoder 101 from accessing a shared memory 140 while an SF reading unit 101 is reading, from the shared memory 140, SF pixel data which is information about respective cells to be lit in a plurality of subfields. On the other hand, the control unit 104 permits the moving picture decoder 101 to access the shared memory 140 while the SF reading unit 101 is not reading the SF pixel data from the shared memory 140, that is to say, during a sustain discharge period.

Abstract: A microcomputer with a built-in flash memory is obtained in which the flash memory can be properly rewritten with a rewrite program kept placed on the flash memory and without requiring additional complicated control circuitry. On accepting an erase/write command which constitutes a rewrite command, a flash memory module (2) outputs to a flash memory control circuit (3) a ready status signal RYIBY indicative of a busy state during execution of the series of processing. When the ready status signal RYIBY indicates the busy state, the flash memory control circuit (3) outputs a hold signal HOLD at active “H,” in order to inhibit a CPU (1) from accessing the flash memory module (2). When the ready status signal RYIBY has recovered the ready state, the flash memory control circuit (3) outputs the hold signal HOLD at “L” to allow the CPU (1) to access the flash memory module (2).

Abstract: Redundant circuits 11 to 15 are provided in correspondence to memory blocks 1 to 5, respectively. Bit lines BL0 to BL15 are located across the memory blocks. Spare bit lines SBL1 and SBL2 are located across the redundant circuits 11 to 15. When a memory cell failure occurs in the memory block 5 except a predetermined memory block (for example, a boot block) 2 and when the bit line BL8 corresponding to the memory cell failure is replaced with the spare bit line SBL1, each of switches 56 and 76 is put into an on state in correspondence to the spare bit line SBL1. Furthermore, each of switches 48 and 88 is put into the on state in correspondence to the bit line BL8. As a result, the spare bit line SBL1 turns the redundant circuit 12 corresponding to the memory block 2, to be connected to the memory block 2.

Abstract: A semiconductor device has a program storage unit and an A/D converter which converts an analog signal inputted from an analog to digital (A/D) conversion input terminal into a digital signal. The semiconductor device is provided with a withstand voltage anomaly test terminal and a selection unit which is; actuated by a program in the program storage unit that selects the A/D conversion input terminal at the time of normal operation; and selects the withstand voltage anomaly test terminal at the time of test operation. A potential signal of the withstand voltage anomaly test terminal at the time of test operation is detected as a digital value by the A/D converter based on the program in the program storage unit so that a judgment is made as normality or anomaly.

Abstract: A microcomputer with a built-in flash memory is obtained in which the flash memory can be properly rewritten with a rewrite program kept placed on the flash memory and without requiring additional complicated control circuitry. On accepting an erase/write command which constitutes a rewrite command, a flash memory module (2) outputs to a flash memory control circuit (3) a ready status signal RYIBY indicative of a busy state during execution of the series of processing. When the ready status signal RYIBY indicates the busy state, the flash memory control circuit (3) outputs a hold signal HOLD at active “H,” in order to inhibit a CPU (1) from accessing the flash memory module (2). When the ready status signal RYIBY has recovered the ready state, the flash memory control circuit (3) outputs the hold signal HOLD at “L” to allow the CPU (1) to access the flash memory module (2).

Abstract: Redundant circuits 11 to 15 are provided in correspondence to memory blocks 1 to 5, respectively. Bit lines BL0 to BL15 are located across the memory blocks. Spare bit lines SBL1 and SBL2 m are located across the redundant circuits 11 to 15. When a memory cell failure occurs in the memory block 5 except a predetermined memory block (for example, a boot block) 2 and when the bit line BL8 corresponding to the memory cell failure is replaced with the spare bit line SBL1, each of switches 56 and 76 is put into an on state in correspondence to the spare bit line SBL1. Furthermore, each of switches 48 and 88 is put into the on state in correspondence to the bit line BL8. As a result, the spare bit line SBL1 turns the redundant circuit 12 corresponding to the memory block 2, to be connected to the memory block 2.