Patents by Inventor Naoki Sakura

Naoki Sakura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11505742
    Abstract: The purpose of the present invention to provide semiconductor nanoparticles substantially containing no Cd, and which have an increased absorption coefficient to blue light while maintaining high stability. Semiconductor nanoparticles having a core containing at least In and P, and a shell having one or more layers, wherein at least one layer of the shell is ZnSeTe (wherein Te/(Se+Te)=0.03 to 0.50); and the semiconductor nanoparticles cause, when the semiconductor nanoparticles are dispersed in a dispersion medium to yield a dispersion liquid with a concentration of 1 mg/mL in inorganic mass, the dispersion liquid to have an absorbance of 0.9 or higher with respect to light having a wavelength of 450 nm at an optical path length of 1 cm.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: November 22, 2022
    Assignee: SHOEI CHEMICAL INC.
    Inventors: Takafumi Moriyama, Hirokazu Sasaki, Makoto Kido, Keisuke Matsuura, Yuko Mitsuka, Naoki Sakura
  • Publication number: 20220184572
    Abstract: Provided is a method for producing particles, the method including a particle generating step of forming a product particle flow including target product particles by heating a segmented reaction raw material liquid flow divided into segments by a gas for segmentation under applying pressure at a pressure P1 (MPa) and at a heating temperature T (° C.) to react the raw material for particle formation to generate the target product particles, in which, at the particle generating step, (Vd/Vc) is 0.200 to 7.00 and the pressure P1 at the particle generating step is 2.0 times or more a vapor pressure P2 (MPa) of a solvent at the heating temperature T. According to the present invention, a method for producing particles having a narrow particle size distribution with high production efficiency can be provided.
    Type: Application
    Filed: February 26, 2020
    Publication date: June 16, 2022
    Inventors: Naoki Sakura, Hirokazu Sasaki
  • Patent number: 11145792
    Abstract: The purpose of the present invention to provide a wavelength conversion layer containing semiconductor nanoparticles substantially containing no Cd, and which have an increased absorption coefficient to blue light while maintaining high stability. A wavelength conversion layer containing semiconductor nanoparticles, wherein the wavelength conversion layer can convert light having a wavelength of 450 nm to light having a peak wavelength of 500 nm to 550 nm, or light having a peak wavelength of 600 nm to 660 nm; each of the semiconductor nanoparticles contained in the wavelength conversion layer has a core and a shell having one or more layers; the core contains In and P; and at least one layer of the shell is ZnXTe (wherein X represents Se or S, or both Se and S).
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: October 12, 2021
    Assignee: SHOEI CHEMICAL INC.
    Inventors: Takafumi Moriyama, Hirokazu Sasaki, Makoto Kido, Keisuke Matsuura, Yuko Mitsuka, Naoki Sakura
  • Publication number: 20200079997
    Abstract: The purpose of the present invention to provide semiconductor nanoparticles substantially containing no Cd, and which have an increased absorption coefficient to blue light while maintaining high stability. Semiconductor nanoparticles having a core containing at least In and P, and a shell having one or more layers, wherein at least one layer of the shell is ZnSeTe (wherein Te/(Se+Te)=0.03 to 0.50); and the semiconductor nanoparticles cause, when the semiconductor nanoparticles are dispersed in a dispersion medium to yield a dispersion liquid with a concentration of 1 mg/mL in inorganic mass, the dispersion liquid to have an absorbance of 0.9 or higher with respect to light having a wavelength of 450 nm at an optical path length of 1 cm.
    Type: Application
    Filed: September 5, 2019
    Publication date: March 12, 2020
    Inventors: Takafumi Moriyama, Hirokazu Sasaki, Makoto Kido, Keisuke Matsuura, Yuko Mitsuka, Naoki Sakura
  • Publication number: 20200083406
    Abstract: The purpose of the present invention to provide a wavelength conversion layer containing semiconductor nanoparticles substantially containing no Cd, and which have an increased absorption coefficient to blue light while maintaining high stability. A wavelength conversion layer containing semiconductor nanoparticles, wherein the wavelength conversion layer can convert light having a wavelength of 450 nm to light having a peak wavelength of 500 nm to 550 nm, or light having a peak wavelength of 600 nm to 660 nm; each of the semiconductor nanoparticles contained in the wavelength conversion layer has a core and a shell having one or more layers; the core contains In and P; and at least one layer of the shell is ZnXTe (wherein X represents Se or S, or both Se and S).
    Type: Application
    Filed: September 5, 2019
    Publication date: March 12, 2020
    Inventors: Takafumi Moriyama, Hirokazu Sasaki, Makoto Kido, Keisuke Matsuura, Yuko Mitsuka, Naoki Sakura
  • Publication number: 20190333706
    Abstract: A can for an electrolytic capacitor is disclosed. In an embodiment a can for an electrolytic capacitor includes a bottom including a first area and a second area, wherein the first area is recessed relative to the second area at an outer surface of the bottom of the can.
    Type: Application
    Filed: March 15, 2017
    Publication date: October 31, 2019
    Inventors: Róbert Bösze, Tamás Lakatár, Naoki Sakura, Ottó Klug, László Gál, Achim Müller
  • Patent number: 8610237
    Abstract: A semiconductor apparatus includes a semiconductor chip, a lead frame that has a first surface having the semiconductor chip mounted thereover and a second surface opposite to the first surface, a bonding wire that couples the semiconductor chip and the lead frame, and a high dielectric constant layer that is disposed over a surface of the lead frame opposite to a surface having the semiconductor chip mounted thereover and that has a relative permittivity of 5 or more. The lead frame includes a source electrode lead coupled to the source of a semiconductor device formed over the semiconductor chip and a source-wire junction at which the source electrode lead and the bonding wire are coupled together. The high dielectric layer is disposed in a region including at least a position corresponding to the source-wire junction over the second surface of the lead frame.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: December 17, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Naoki Sakura
  • Publication number: 20130062788
    Abstract: A semiconductor apparatus includes a semiconductor chip, a lead frame that has a first surface having the semiconductor chip mounted thereover and a second surface opposite to the first surface, a bonding wire that couples the semiconductor chip and the lead frame, and a high-dielectric layer that is disposed over a surface of the lead frame opposite to a surface having the semiconductor chip mounted thereover and that has a relative permittivity of 5 or more. The lead frame includes a source electrode lead coupled to the source of a semiconductor device formed over the semiconductor chip and a source-wire junction at which the source electrode lead and the bonding wire are coupled together. The high-dielectric layer is disposed in a region including at least a position corresponding to the source-wire junction over the second surface of the lead frame.
    Type: Application
    Filed: July 19, 2012
    Publication date: March 14, 2013
    Inventor: Naoki SAKURA
  • Publication number: 20110215452
    Abstract: A semiconductor package includes a semiconductor device and a substrate over which the semiconductor device is mounted, wherein the substrate includes: an internal ground electrode, formed in the one side of the substrate, which is connected to the semiconductor device; two external ground electrodes, located at the opposite side of the substrate opposite to the one side of the substrate, which are electrically connected to the internal ground electrode; at least one sub-ground electrode, located between the two external ground electrodes, when seen in a plan view, and located at the opposite side of the substrate, which is electrically connected to the internal ground electrode; an internal input electrode, formed in the one side of the substrate, which is connected to the semiconductor device; and an internal output electrode, formed in the one of the substrate, which is connected to the semiconductor device.
    Type: Application
    Filed: March 7, 2011
    Publication date: September 8, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Naoki SAKURA
  • Patent number: 7851884
    Abstract: A FET exhibiting excellent uniformity and productivity and having a low noise figure and high associated gain as high-frequency performance, a semiconductor chip having this FET and a semiconductor device having the semiconductor chip. The FET includes a GaAs substrate on which are built up an i-type GaAs layer, an i-type InGaAs two-dimensional electron gas layer and an n-type AlGaAs electron supply layer. A gate electrode is provided on and in linear Schottky contact with the n-type AlGaAs electron supply layer. A n-type InGaP etching stop layer and then an n-type GaAs contact layer at the same lateral position are built up on the n-type AlGaAs electron supply layer, these being spaced away from both sides of the gate electrode. A source electrode and a drain electrode are provided on the n-type GaAs contact layer and are spaced away from edges of the contact layer as electrodes that make band-shaped ohmic contact.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: December 14, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Shuji Asai, Akira Fujihara, Makoto Matsunoshita, Naoki Sakura, Seiji Ichikawa
  • Publication number: 20090288852
    Abstract: An electronic device of the present invention has a substrate; an electro-conductive pattern (electrodes) provided over the substrate; a semiconductor chip mounted over the substrate, and electrically connected with the electrodes; a resin cap provided over the substrate and composed of two or more resin layers to hollow-sealing the semiconductor chip; and an adhesive layer (metal-resin adhesion maintenance layer) bonding the resin cap with the electrode.
    Type: Application
    Filed: April 27, 2009
    Publication date: November 26, 2009
    Applicant: NEC Electronics Corporation
    Inventors: Tomoaki Hirokawa, Makoto Matsunoshita, Yuji Kakuta, Naoki Sakura
  • Publication number: 20090078966
    Abstract: A FET exhibiting excellent uniformity and productivity and having a low noise figure and high associated gain as high-frequency performance, a semiconductor chip having this FET and a semiconductor device having the semiconductor chip. The FET includes a GaAs substrate on which are built up an i-type GaAs layer, an i-type InGaAs two-dimensional electron gas layer and an n-type AlGaAs electron supply layer. A gate electrode is provided on and in linear Schottky contact with the n-type AlGaAs electron supply layer. A n-type InGaP etching stop layer and then an n-type GaAs contact layer at the same lateral position are built up on the n-type AlGaAs electron supply layer, these being spaced away from both sides of the gate electrode. A source electrode and a drain electrode are provided on the n-type GaAs contact layer and are spaced away from edges of the contact layer as electrodes that make band-shaped ohmic contact.
    Type: Application
    Filed: September 24, 2008
    Publication date: March 26, 2009
    Applicant: NEC Electronics Corporation
    Inventors: Shuji Asai, Akira Fujihara, Makoto Matsunoshita, Naoki Sakura, Seiji Ichikawa
  • Patent number: 6372613
    Abstract: In a semiconductor device, a gate electrode is formed by sequentially forming a Schottky metal film, a barrier metal film, and a low-resistance metal film from the lower side. The Schottky metal film or barrier metal film has a gap in a lower gate vertical portion. The gap is closed at its upper and lower portions. The overlaying low-resistance metal film does not extend into the lower gate vertical portion. A method for this semiconductor device is also disclosed.
    Type: Grant
    Filed: May 4, 1999
    Date of Patent: April 16, 2002
    Assignee: NEC Corporation
    Inventor: Naoki Sakura
  • Publication number: 20010046759
    Abstract: In a semiconductor device, a gate electrode is formed by sequentially forming a Schottky metal film, a barrier metal film, and a low-resistance metal film from the lower side. The Schottky metal film or barrier metal film has a gap in a lower gate vertical portion. The gap is closed at its upper and lower portions. The overlayering low-resistance metal film does not extend into the lower gate vertical portion. A method for this semiconductor device is also disclosed.
    Type: Application
    Filed: May 4, 1999
    Publication date: November 29, 2001
    Inventor: NAOKI SAKURA
  • Patent number: 5925902
    Abstract: In a semiconductor device, a gate electrode is formed by sequentially forming a Schottky metal film, a barrier metal film, and a low-resistance metal film from the lower side. The Schottky metal film or barrier metal film has a gap in a lower gate vertical portion. The gap is closed at its upper and lower portions. The overlaying low-resistance metal film does not extend into the lower gate vertical portion. A method for this semiconductor device is also disclosed.
    Type: Grant
    Filed: May 29, 1998
    Date of Patent: July 20, 1999
    Assignee: Nec Corporation
    Inventor: Naoki Sakura
  • Patent number: 5869365
    Abstract: In a method of manufacturing a semiconductor device, an operating layer and a light-shielding film are sequentially formed to form a recess step on a semiconductor substrate. A first photoresist film is formed on the light-shielding film. The light-shielding film is patterned using the photoresist film as a mask to form a gate electrode formation opening portion. A metal film is formed on the entire surface including the opening portion. The metal film is selectively etched using, as a mask, a second photoresist film formed on the metal film, thereby forming a gate electrode having a T shape in the longitudinal section. The second photoresist film is removed. The light-shielding film is removed.
    Type: Grant
    Filed: October 2, 1997
    Date of Patent: February 9, 1999
    Assignee: NEC Corporation
    Inventor: Naoki Sakura
  • Patent number: 5763143
    Abstract: Tension takes place in a surface of a photo-resist mask due to a shrinkage in a post-development bake, and a recess formed in the photo-resist mask takes up the tension so as to maintain the adhesion to a semiconductor substrate and prevent a resist pattern from undesirable deformation.
    Type: Grant
    Filed: December 13, 1995
    Date of Patent: June 9, 1998
    Assignee: NEC Corporation
    Inventor: Naoki Sakura
  • Patent number: 4374828
    Abstract: A class of three substances has been isolated in highly purified form and in substantially pure form by utilizing thymus tissue as a source material. These three substances are designated thymone A, thymone B and thymone C. Thymones A and B are new peptides which yield approximately 13 and 14 individual amino acid moieties, respectively, on acid hydrolysis. Thymones A and B are chemically characterized by electrophoretic and chromatographic values which are appropriate for substances which are substantially pure. Thymone C was highly purified and its biological activity was reproducibly detected and measured. Thymones A, B and C stimulate the proliferation of lymphocytes. Thymone A stimulates the formation of cyclic adenosine monophosphate. Thymone B stimulates the formation of cyclic guanosine monophosphate.
    Type: Grant
    Filed: November 17, 1980
    Date of Patent: February 22, 1983
    Assignee: Board of Reagents, The University of Texas System
    Inventors: Karl Folkers, Teresa M. Kubiak, Henryk M. Stepien, Naoki Sakura