Abstract: A magnetic recording and reproduction apparatus, includes a circuit for changing a reference amplitude value of a Viterbi detector. The circuit is used to record and reproduce data with the reference amplitude value displaced from a reference value, thereby measuring the data error rate. Displacement of the reference amplitude from a reference value increases the data error rate, and therefore the data error rate can be measured within a short time. A data error rate with the reference amplitude equal to a reference value is estimated from the data error rate measurement, thereby making it possible to evaluate the degree of accuracy of a magnetic recording and reproduction apparatus. The data error rate is measured with the reference amplitude of the Viterbi detector displaced from a reference value while changing the equalization coefficient value of a waveform equalizer, the cut-off frequency of a low-pass filter and the write precompensation amount of a write precompensation circuit.

Abstract: The object of the invention is to provide an equalizer capable of generating an equalized output compensated in the non-linearity of the signal reproduced by an MR head and a reliable high-density magnetically recorded-signal reproducer. An equalizer of an FIR-type filter structure comprises a plurality of delay elements for delaying input signals by a certain period, a plurality of coefficient processing units provided to input or output taps of the delay elements, and an adder for obtaining the sum of the outputs of the coefficient processing units, in which the distortion of the reproduced waveform can be corrected by a relatively simple circuit structure by comparing the signal value inputted to the coefficient processing unit from each tap with a predetermined threshold level and changing the signal value and a coefficient value to be multiplied in accordance with the comparison result.

Abstract: A signal processing circuit for a magnetic recording/reproducing apparatus, including at least an AGC, a PLL, a LPF, an equalizer circuit and a detection circuit, wherein a coefficient compensation circuit is formed by defining a constitution of the equalizer circuit, an error detection circuit is provided which operates by receiving input from the detection circuit, and the LSI is formed by a plurality of analog and digital chips, and the analog and digital chips are connected by current-output type D/A converters connected to at least the AGC and the PLL.

Abstract: A phase lock loop system includes: a phase detecting circuit which operates on the basis of a signal waveform; a current output circuit for generating a current value from a phase difference detected by the phase detecting circuit; a filter which is constructed by only a resistor in a phase locked state by a synchronizing signal and by a capacitor and the resistor upon phase following state; and a voltage controlled oscillator for controlling an oscillation frequency by a voltage output of the filter. The phase lock loop system operates as a primary phase lock loop circuit in the phase locked state by the synchronizing signal and operates as a secondary phase lock loop circuit upon phase following state.

Abstract: A data recording/reproducing apparatus and method therefor having a Viterbi decoder which stores operation result values of an inputted reproduced signal and the reference value when the peak value of the reproduced signal is updated, compares this value with the reproduced signal in amplitude, updates the stored value when the result satisfies the predetermined condition, detects a change in the polarity of the comparison result, controls the clock counter depending on the status of the peak value updating signal, sets 1 in the shift register at the position indicated by the counter according to the detected polarity inversion signal when the peak value is updated, and accordingly makes the updating and detecting operations independent of operations of addition and subtraction of the current reproduced signal and reference value and operations of addition and subtraction of amplitude comparison.

Abstract: A decision feedback equalization circuit which can be operated at a high speed with a low cost as well as a high-speed digital data communication system and a high-speed digital data recording system using the equalization circuit are disclosed. The decision feedback equalization circuit has data memories which correspond to the number of available values in decision result and in which feedback signals corresponding to all the next decision results are previously prepared as candidates so that a suitable one of the feedback signal candidates is selected and fed back based on the obtained decision result, thus realizing high-speed operation of a feedback loop.

Abstract: An optical disk device which uses a light spot for reproducing data, including photodetector, a decoder, and a non-linear equalizer provided between the photodetector and the decoder for correcting non-linear distortions in a reproduced signal from an optical disk. The non-linear equalizer includes a linear equalizer and a decision feedback equalizer provided after the linear equalizer. The non-linear equalizer includes a detector for detecting a signal on the basis of the output of the linear equalizer with the output of the detector being input to the decision feedback equalizer, the output of which is input to the detector along with the output of the linear equalizer in an additive manner.

Abstract: A signal processing apparatus for converting an analog signal to a digital signal and processing the digital signal. In particular, a digital filter for performing processing at high speed is implemented by using an integrated circuit of low power consumption. The signal processing apparatus includes a circuit for comparing an input analog signal with each voltage of a plurality of analog reference voltages and generating a thermometer code Tc depending upon the analog input signal, a decoder for detecting a change point of the thermometer code Tc, and a plurality of memory circuits having output signal lines of the decoder as word selection lines. The product of an input signal value corresponding to each word selection line and a predetermined filter coefficient is stored in the corresponding word of the memory circuits. The memories are used as look-up tables.

Abstract: When image information obtained on the basis of an NMR signal, e.g. MRI, is acquired, a radio frequency pulse is set so that a strong signal can be obtained particularly from a portion of interest among the sample. To accomplish this object, the occurrence of signals from portions of the sample other than the selected portion of interest is inhibited in advance of obtaining information (an image) of the sample. Various radio frequency pulses are then irradiated to the sample and a suitable radio frequency pulse is determined on the basis of the resulting signal.